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| author | Kulkarni, Ganapatrao <Ganapatrao.Kulkarni@cavium.com> | 2018-12-06 11:51:31 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-06 13:03:17 +0000 |
| commit | 69c32972d59388c041268e8206e8eb1acff29b9a (patch) | |
| tree | 1d1e477db9250533e5f6cb26a9cb4c74097ff487 /drivers/perf/Kconfig | |
| parent | d6310a3f3396e004bdb7a76787a2a3bbc643d0b7 (diff) | |
| download | linux-69c32972d59388c041268e8206e8eb1acff29b9a.tar.bz2 | |
drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
counters. All counters lack overflow interrupt and are
sampled periodically.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
[will: consistent enum cpuhp_state naming]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf/Kconfig')
| -rw-r--r-- | drivers/perf/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 08ebaf7cca8b..af9bc178495d 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -87,6 +87,15 @@ config QCOM_L3_PMU Adds the L3 cache PMU into the perf events subsystem for monitoring L3 cache events. +config THUNDERX2_PMU + tristate "Cavium ThunderX2 SoC PMU UNCORE" + depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA + default m + help + Provides support for ThunderX2 UNCORE events. + The SoC has PMU support in its L3 cache controller (L3C) and + in the DDR4 Memory Controller (DMC). + config XGENE_PMU depends on ARCH_XGENE bool "APM X-Gene SoC PMU" |