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authorLucas Stach <l.stach@pengutronix.de>2014-07-23 19:52:38 +0200
committerBjorn Helgaas <bhelgaas@google.com>2014-09-04 14:58:48 -0600
commit4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6 (patch)
tree2b1532fb6581a400bcf6e28a2a275cc169eccb44 /drivers/pci
parentb14a3d1784a9252aa3bbe0bb9d14588be32f18a1 (diff)
downloadlinux-4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6.tar.bz2
PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. [bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-designware.c11
-rw-r--r--drivers/pci/host/pcie-designware.h1
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 76d3d8e1f33b..561fa30862ae 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
+ ret = of_pci_parse_bus_range(np, &pp->busn);
+ if (ret < 0) {
+ pp->busn.name = np->name;
+ pp->busn.start = 0;
+ pp->busn.end = 0xff;
+ pp->busn.flags = IORESOURCE_BUS;
+ dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
+ ret, &pp->busn);
+ }
+
if (!pp->dbi_base) {
pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
resource_size(&pp->cfg));
@@ -794,6 +804,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
+ pci_add_resource(&sys->resources, &pp->busn);
return 1;
}
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3e84e0ae0851..a476e60993cb 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -48,6 +48,7 @@ struct pcie_port {
struct resource cfg;
struct resource io;
struct resource mem;
+ struct resource busn;
struct pcie_port_info config;
int irq;
u32 lanes;