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authorKishon Vijay Abraham I <kishon@ti.com>2019-03-25 15:09:44 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-05-01 15:50:13 +0100
commitfc9a77040b04c05f036515f40aa7cf4b9c91defd (patch)
tree67e0f2cb014853584bdd062246c79ae02a7e6ff4 /drivers/pci
parent23284ad677a94f26afc92017d540ccaf26c1a581 (diff)
downloadlinux-fc9a77040b04c05f036515f40aa7cf4b9c91defd.tar.bz2
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
Configure the Resizable BAR capability to advertise the smallest size (1MB) for a couple of reasons: - Host side resource allocation of BAR fails for larger sizes - Endpoint function driver does not allocate memory for all supported sizes in the Resizable BAR capability. If and when there is a usecase required to add more flexibility using the Resizable BAR capability, this can be revisited. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/controller/dwc/pcie-designware-ep.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 74477ad7467f..0c208b9bda43 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc);
}
+static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
+{
+ u32 header;
+ int pos = PCI_CFG_SPACE_SIZE;
+
+ while (pos) {
+ header = dw_pcie_readl_dbi(pci, pos);
+ if (PCI_EXT_CAP_ID(header) == cap)
+ return pos;
+
+ pos = PCI_EXT_CAP_NEXT(header);
+ if (!pos)
+ break;
+ }
+
+ return 0;
+}
+
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
{
+ int i;
int ret;
+ u32 reg;
void *addr;
+ unsigned int nbars;
+ unsigned int offset;
struct pci_epc *epc;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct device *dev = pci->dev;
@@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
+ offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+ if (offset) {
+ reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
+ nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
+ PCI_REBAR_CTRL_NBAR_SHIFT;
+
+ dw_pcie_dbi_ro_wr_en(pci);
+ for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
+ dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
+ dw_pcie_dbi_ro_wr_dis(pci);
+ }
+
dw_pcie_setup(pci);
return 0;