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authorAlex Williamson <alex.williamson@redhat.com>2013-08-08 14:10:13 -0600
committerBjorn Helgaas <bhelgaas@google.com>2013-08-14 15:25:17 -0600
commitde0c548c33429cc78fd47a3c190c6d00b0e4e441 (patch)
tree0c9fef4deaee4cb6195d5c1e6dd5e4d4c779e98c /drivers/pci
parenta6cbaadea0af9b4aa6eee2882f2aa761ab91a4f8 (diff)
downloadlinux-de0c548c33429cc78fd47a3c190c6d00b0e4e441.tar.bz2
PCI: Tune secondary bus reset timing
The PCI spec indicates that with stable power, reset needs to be asserted for a minimum of 1ms (Trst). We should be able to assume stable power for a Hot Reset, but we add another millisecond as a fudge factor to make sure the reset is seen on the bus for at least a full 1ms. After reset is de-asserted we must wait for devices to complete initialization. The specs refer to this as "recovery time" (Trhfa). For PCI this is 2^25 clock cycles or 2^26 for PCI-X. For minimum bus speeds, both of those come to 1s. PCIe "softens" this requirement with the Configuration Request Retry Status (CRS) completion status. Theoretically we could use CRS to shorten the wait time. We don't make use of that here, using a fixed 1s delay to allow devices to re-initialize. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index deb7fa9cc638..ea5e70486174 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3230,11 +3230,23 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
- msleep(100);
+ /*
+ * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
+ * this to 2ms to ensure that we meet the minium requirement.
+ */
+ msleep(2);
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
- msleep(100);
+
+ /*
+ * Trhfa for conventional PCI is 2^25 clock cycles.
+ * Assuming a minimum 33MHz clock this results in a 1s
+ * delay before we can consider subordinate devices to
+ * be re-initialized. PCIe has some ways to shorten this,
+ * but we don't make use of them yet.
+ */
+ ssleep(1);
}
EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);