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authorBjorn Helgaas <bhelgaas@google.com>2018-06-08 08:48:47 -0500
committerBjorn Helgaas <helgaas@kernel.org>2018-06-11 08:11:39 -0500
commit4696b828ca3781deebc3f61d50978d5c8c5be405 (patch)
tree50151d3abf5e2936adc47a8ee375c66d81ac7672 /drivers/pci/pcie/Kconfig
parentadc1f22f5a8664b07734a23a8d9bb82a38c0d043 (diff)
downloadlinux-4696b828ca3781deebc3f61d50978d5c8c5be405.tar.bz2
PCI/AER: Hoist aerdrv.c, aer_inject.c up to drivers/pci/pcie/
Hoist aerdrv.c, aer_inject.c up to drivers/pci/pcie/ so they're next to other PCIe service drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
Diffstat (limited to 'drivers/pci/pcie/Kconfig')
-rw-r--r--drivers/pci/pcie/Kconfig37
1 files changed, 36 insertions, 1 deletions
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index b12e28b3d8f9..4a8e26a2b012 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -23,7 +23,42 @@ config HOTPLUG_PCI_PCIE
When in doubt, say N.
-source "drivers/pci/pcie/aer/Kconfig"
+config PCIEAER
+ bool "Root Port Advanced Error Reporting support"
+ depends on PCIEPORTBUS
+ select RAS
+ default y
+ help
+ This enables PCI Express Root Port Advanced Error Reporting
+ (AER) driver support. Error reporting messages sent to Root
+ Port will be handled by PCI Express AER driver.
+
+config PCIEAER_INJECT
+ tristate "PCIe AER error injector support"
+ depends on PCIEAER
+ default n
+ help
+ This enables PCI Express Root Port Advanced Error Reporting
+ (AER) software error injector.
+
+ Debugging PCIe AER code is quite difficult because it is hard
+ to trigger various real hardware errors. Software based
+ error injection can fake almost all kinds of errors with the
+ help of a user space helper tool aer-inject, which can be
+ gotten from:
+ http://www.kernel.org/pub/linux/utils/pci/aer-inject/
+
+#
+# PCI Express ECRC
+#
+config PCIE_ECRC
+ bool "PCI Express ECRC settings control"
+ depends on PCIEAER
+ help
+ Used to override firmware/bios settings for PCI Express ECRC
+ (transaction layer end-to-end CRC checking).
+
+ When in doubt, say N.
#
# PCI Express ASPM