summaryrefslogtreecommitdiffstats
path: root/drivers/pci/pci.h
diff options
context:
space:
mode:
authorBjorn Helgaas <bhelgaas@google.com>2021-09-02 14:56:44 -0500
committerBjorn Helgaas <bhelgaas@google.com>2021-09-02 14:56:44 -0500
commit739c4747a25af3a2571f69e4709f2b476a17d5d4 (patch)
tree6eb232ecbe51c0d5156804e211b6cd25dd3cbcf0 /drivers/pci/pci.h
parent74797618e2022dfcd923f1ea8903ba4959f746a4 (diff)
parent0da14a19493da0f9b4c5ee5930ab05a4c61f5883 (diff)
downloadlinux-739c4747a25af3a2571f69e4709f2b476a17d5d4.tar.bz2
Merge branch 'pci/misc'
- Add pci_numachip_init() declaration (Krzysztof Wilczyński) - Allocate pci_dev_str_match_path() string atomically (Dan Carpenter) - Drop error message when Precision Time Measurement supported but not enabled (Jakub Kicinski) - Correct the pci_iomap.h header guard #endif comment (Jonathan Cameron) - Add schedule point in proc_bus_pci_read() (Krzysztof Wilczyński) - Make saved capability state private to core (Bjorn Helgaas) - Sync __pci_register_driver() stub for CONFIG_PCI=n (Andy Shevchenko) - Convert sta2x11 from PCI-DMA-API to generic DMA-API (Christophe JAILLET) * pci/misc: x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API PCI: Sync __pci_register_driver() stub for CONFIG_PCI=n PCI: Make saved capability state private to core PCI: Add schedule point in proc_bus_pci_read() PCI: Correct the pci_iomap.h header guard #endif comment PCI/PTM: Remove error message at boot PCI: Fix pci_dev_str_match_path() alloc while atomic bug x86/PCI: Add pci_numachip_init() declaration # Conflicts: # include/linux/pci.h
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r--drivers/pci/pci.h23
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 05b7e7e04246..78557d2c6612 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -38,6 +38,27 @@ void pci_init_reset_methods(struct pci_dev *dev);
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
int pci_bus_error_reset(struct pci_dev *dev);
+struct pci_cap_saved_data {
+ u16 cap_nr;
+ bool cap_extended;
+ unsigned int size;
+ u32 data[];
+};
+
+struct pci_cap_saved_state {
+ struct hlist_node next;
+ struct pci_cap_saved_data cap;
+};
+
+void pci_allocate_cap_save_buffers(struct pci_dev *dev);
+void pci_free_cap_save_buffers(struct pci_dev *dev);
+int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
+int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
+ u16 cap, unsigned int size);
+struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
+struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
+ u16 cap);
+
#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
#define PCI_PM_D3HOT_WAIT 10 /* msec */
#define PCI_PM_D3COLD_WAIT 100 /* msec */
@@ -101,8 +122,6 @@ void pci_pm_init(struct pci_dev *dev);
void pci_ea_init(struct pci_dev *dev);
void pci_msi_init(struct pci_dev *dev);
void pci_msix_init(struct pci_dev *dev);
-void pci_allocate_cap_save_buffers(struct pci_dev *dev);
-void pci_free_cap_save_buffers(struct pci_dev *dev);
bool pci_bridge_d3_possible(struct pci_dev *dev);
void pci_bridge_d3_update(struct pci_dev *dev);
void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);