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| author | Mohit Kumar <mohit.kumar@st.com> | 2014-04-16 10:23:28 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-04-16 10:23:28 -0600 |
| commit | c23fdc7da4853c25509255419bf88ed94cd42a5b (patch) | |
| tree | 5dedd9f291b9cd29f4cf777b2d6fece4f6e421a8 /drivers/pci/host | |
| parent | 140ab6452c42174d20e2fdd27ed73b889cd86500 (diff) | |
| download | linux-c23fdc7da4853c25509255419bf88ed94cd42a5b.tar.bz2 | |
PCI: designware: Fix comment for setting number of lanes
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 509a29d84509..8909e7748e67 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; - /* set the number of lines as 4 */ + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { |