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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2018-05-09 09:12:59 +0800 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-05-11 10:36:02 +0100 |
| commit | cf590b07839133146842d2d3d9a68f804c2edc4b (patch) | |
| tree | 9ab6f6e03049bb8f286419ca177abbfa67a79631 /drivers/pci/host/Kconfig | |
| parent | 2ca25bd7472fba955081bcf03a9b3d9c3b77dec4 (diff) | |
| download | linux-cf590b07839133146842d2d3d9a68f804c2edc4b.tar.bz2 | |
PCI: rockchip: Add EP driver for Rockchip PCIe controller
Add support for the Rockchip PCIe controller in endpoint mode;
it currently supports up to 32 regions with each region spanning
at least 1MB as per TRM.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/host/Kconfig')
| -rw-r--r-- | drivers/pci/host/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index f2d8cab8fe5e..0d8b21b690ce 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -194,6 +194,18 @@ config PCIE_ROCKCHIP_HOST There is 1 internal PCIe port available to support GEN2 with 4 slots. +config PCIE_ROCKCHIP_EP + bool "Rockchip PCIe endpoint controller" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + depends on PCI_ENDPOINT + select MFD_SYSCON + select PCIE_ROCKCHIP + help + Say Y here if you want to support Rockchip PCIe controller in + endpoint mode on Rockchip SoC. There is 1 internal PCIe port + available to support GEN2 with 4 slots. + config PCIE_MEDIATEK bool "MediaTek PCIe controller" depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST) |