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authorBjorn Helgaas <bhelgaas@google.com>2020-06-04 12:59:15 -0500
committerBjorn Helgaas <bhelgaas@google.com>2020-06-04 12:59:15 -0500
commitb9fcf4910b72dd4d94b36989df5d6bcf7795c18d (patch)
treecf1d51fe10b942f98b72c3bc945dbc6e2a628f67 /drivers/pci/controller/dwc/Kconfig
parent712879510fa4930b65748046426ac4a730512bba (diff)
parent8d7e33d6811fbd24d3a1476a1b481b704975352a (diff)
downloadlinux-b9fcf4910b72dd4d94b36989df5d6bcf7795c18d.tar.bz2
Merge branch 'remotes/lorenzo/pci/dwc'
- Simplify computation of msix_tbl (Jiri Slaby) - Make hisi_pcie_platform_ops static (Zou Wei) - Warn about resources above 4G (Alan Mikhak) - Make intel_pcie_cpu_addr() static (Jason Yan) - Use devm_platform_ioremap_resource_byname() to simplify code and improve error checking (Wei Yongjun) - Fix inner MSI IRQ domain registration so it doesn't confuse debugfs (Marc Zyngier) - Don't use FAST_LINK_MODE on meson (Marc Zyngier) - Add Socionext UniPhier Pro5 PCIe endpoint controller driver and DT description (Kunihiko Hayashi) * remotes/lorenzo/pci/dwc: PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver dt-bindings: PCI: Add UniPhier PCIe endpoint controller description PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_port PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link PCI: dwc: Fix inner MSI IRQ domain registration PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname() PCI: dwc: intel: Make intel_pcie_cpu_addr() static PCI: dwc: Program outbound ATU upper limit register PCI: dwc: Make hisi_pcie_platform_ops static PCI: dwc: Clean up computing of msix_tbl
Diffstat (limited to 'drivers/pci/controller/dwc/Kconfig')
-rw-r--r--drivers/pci/controller/dwc/Kconfig14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ce13fd62d161..044a3761c44f 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -280,15 +280,25 @@ config PCIE_TEGRA194_EP
selected. This uses the DesignWare core.
config PCIE_UNIPHIER
- bool "Socionext UniPhier PCIe controllers"
+ bool "Socionext UniPhier PCIe host controllers"
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && HAS_IOMEM
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
help
- Say Y here if you want PCIe controller support on UniPhier SoCs.
+ Say Y here if you want PCIe host controller support on UniPhier SoCs.
This driver supports LD20 and PXs3 SoCs.
+config PCIE_UNIPHIER_EP
+ bool "Socionext UniPhier PCIe endpoint controllers"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF && HAS_IOMEM
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ help
+ Say Y here if you want PCIe endpoint controller support on
+ UniPhier SoCs. This driver supports Pro5 SoC.
+
config PCIE_AL
bool "Amazon Annapurna Labs PCIe controller"
depends on OF && (ARM64 || COMPILE_TEST)