diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-04-29 14:14:35 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-05-19 00:50:23 -0500 |
| commit | 345f84227b50e90329dd303499024603596566f4 (patch) | |
| tree | 609868e873f374aacdbb58a37db8de4517bf4d8e /drivers/net/ucc_geth.c | |
| parent | 06c4435021f4856261edd01e2691071edeb8fa51 (diff) | |
| download | linux-345f84227b50e90329dd303499024603596566f4.tar.bz2 | |
net/ucc_geth: update riscTx and riscRx in ucc_geth
Change the definition of riscTx and riscRx to unsigned integer instead of
enum, and change their values to support 4 risc allocation if the qe has
4 RISC engines.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/net/ucc_geth.c')
| -rw-r--r-- | drivers/net/ucc_geth.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index 44f8392da117..8287bc19868b 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, u8 num_entries, u32 thread_size, u32 thread_alignment, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, static int return_init_enet_entries(struct ucc_geth_private *ugeth, u32 *p_start, u8 num_entries, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth, u32 __iomem *p_start, u8 num_entries, u32 thread_size, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -2135,6 +2135,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) return -ENOMEM; } + /* read the number of risc engines, update the riscTx and riscRx + * if there are 4 riscs in QE + */ + if (qe_get_num_of_risc() == 4) { + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; + } + ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); if (!ugeth->ug_regs) { if (netif_msg_probe(ugeth)) |