diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2008-12-21 20:19:57 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-12-21 20:19:57 -0800 |
| commit | 69fc405318967c7913e5b55cf3906250a26b49d0 (patch) | |
| tree | 9b885268fd7cf4d9f6170b8791b934bdd44bb2e3 /drivers/net/tg3.c | |
| parent | 027455adacdc142cc018e555ce391014fa227e70 (diff) | |
| download | linux-69fc405318967c7913e5b55cf3906250a26b49d0.tar.bz2 | |
tg3: Remove unused cfgspc device members
This patch removes the pci_bist and pci_hdr_type members from the
device structure and removes the code that references them. They are
not really used.
The patch rounds out the changes by moving the pci_cmd member to plug
a structure hole that would have been created. On 32-bit systems, this
movement removes a subsequent structure hole later in the structure. On
64-bit systems though, the movement merely consolidates two holes into
one larger hole.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9af8c9bb9864..218c11a6ff80 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -12160,7 +12160,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) { }, }; u32 misc_ctrl_reg; - u32 cacheline_sz_reg; u32 pci_state_reg, grc_misc_cfg; u32 val; u16 pci_cmd; @@ -12330,14 +12329,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); - pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ, - &cacheline_sz_reg); - - tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff; - tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff; - tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff; - tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) tp->pdev_peer = tg3_find_peer(tp); @@ -12447,17 +12438,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; + pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, + &tp->pci_cacheline_sz); + pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, + &tp->pci_lat_timer); if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && tp->pci_lat_timer < 64) { tp->pci_lat_timer = 64; - - cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0); - cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8); - cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16); - cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24); - - pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ, - cacheline_sz_reg); + pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, + tp->pci_lat_timer); } if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |