diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-11-02 14:30:40 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-11-02 23:39:11 -0800 |
| commit | 63a14ce449dd6d647de2725809159eb072b2c44f (patch) | |
| tree | d4db22459a237188aefc2c5bc3ee35374443fe1e /drivers/net/phy | |
| parent | 8649f13d2d810406da444a6101906041b796fbde (diff) | |
| download | linux-63a14ce449dd6d647de2725809159eb072b2c44f.tar.bz2 | |
tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
Broadcom 50610M parts changed the default definitions of the RGMII mode
shadow register. The 5785 needs the RGMII mode selection bits [4:3]
cleared.
The default value of the remaining bits in this register are zero.
Rather than unnecessarily burn an extra bit in the dev_flags member in
an attempt to enumerate all possible combinations, this patch take a
more course grained approach and labels the option as "clear all bits".
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/broadcom.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index ace0ccc87a00..5d2a2e90aba8 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -105,6 +105,7 @@ #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) /* LED1 / ~LINKSPD[1] selector */ #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) +#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ @@ -330,6 +331,11 @@ static int bcm54xx_config_init(struct phy_device *phydev) if (err < 0) return err; + if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || + BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && + (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) + bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0); + bcm54xx_phydsp_config(phydev); return 0; |