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authorGrygorii Strashko <grygorii.strashko@ti.com>2017-01-06 14:07:33 -0600
committerDavid S. Miller <davem@davemloft.net>2017-01-07 20:48:14 -0500
commit90225bf0ba35ab43d1e9825c22f3810826c8bfe8 (patch)
treeddc4837e5b27a7abd2d9dfdff5a95b6b8f0b01a7 /drivers/net/ethernet/ti/davinci_cpdma.h
parent7f3b490aaacd789ebc0e26e47b7706547afd0438 (diff)
downloadlinux-90225bf0ba35ab43d1e9825c22f3810826c8bfe8.tar.bz2
net: ethernet: ti: cpsw: add support for descs pool size configuration
The CPSW CPDMA can process buffer descriptors placed as in internal CPPI RAM as in DDR. This patch adds support in CPSW and CPDMA for descs_pool_size mudule parameter, which defines total number of CPDMA CPPI descriptors to be used for both ingress/egress packets processing: - memory size, required for CPDMA descriptor pool, is calculated basing on number of descriptors specified by user in descs_pool_size and CPDMA descriptor size and allocated from coherent memory (CMA area); - CPDMA descriptor pool will be allocated in DDR if pool memory size > internal CPPI RAM or use internal CPPI RAM otherwise; - if descs_pool_size not specified in DT - the default value 256 will be used which will allow to place CPDMA descriptors pool into the internal CPPI RAM (current default behaviour); - CPDMA will ignore descs_pool_size if descs_pool_size = 0 for backward comaptiobility with davinci_emac. descs_pool_size is boot time setting and can't be changed once CPSW/CPDMA is initialized. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/ti/davinci_cpdma.h')
-rw-r--r--drivers/net/ethernet/ti/davinci_cpdma.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h b/drivers/net/ethernet/ti/davinci_cpdma.h
index 4a167db2abab..cb45f8f543d9 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.h
+++ b/drivers/net/ethernet/ti/davinci_cpdma.h
@@ -37,6 +37,7 @@ struct cpdma_params {
int desc_mem_size;
int desc_align;
u32 bus_freq_mhz;
+ u32 descs_pool_size;
/*
* Some instances of embedded cpdma controllers have extra control and