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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-01-07 00:02:52 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-01-09 15:40:56 -0500 |
| commit | 2e653ff0758ae8e47499d588666eb77f6a0fc755 (patch) | |
| tree | f5c1f10f4be612a2920c9a482b6c3cc4ab5bc5cf /drivers/net/ethernet/renesas | |
| parent | bb1d3034449ed08e2ffbf5813a5ad9fa30475359 (diff) | |
| download | linux-2e653ff0758ae8e47499d588666eb77f6a0fc755.tar.bz2 | |
sh_eth: get rid of 'sh_eth_cpu_data::shift_rd0'
After checking all the available manuals, I have enough information to
conclude that the 'shift_rd0' flag is only relevant for the Ether cores
supporting so called "intelligent checksum" (and hence having CSMR) which
is indicated by the 'hw_crc' flag. Since all the relevant SoCs now have
both these flags set, we can at last get rid of the former flag...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/renesas')
| -rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.c | 5 | ||||
| -rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.h | 1 |
2 files changed, 1 insertions, 5 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 9a97cb13029a..6ea30bace685 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -537,7 +537,6 @@ static struct sh_eth_cpu_data r7s72100_data = { .no_ade = 1, .hw_crc = 1, .tsu = 1, - .shift_rd0 = 1, }; static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) @@ -577,7 +576,6 @@ static struct sh_eth_cpu_data r8a7740_data = { .hw_crc = 1, .tsu = 1, .select_mii = 1, - .shift_rd0 = 1, }; /* There is CPU dependent code */ @@ -816,7 +814,6 @@ static struct sh_eth_cpu_data sh7734_data = { .tsu = 1, .hw_crc = 1, .select_mii = 1, - .shift_rd0 = 1, }; /* SH7763 */ @@ -1416,7 +1413,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) * the RFS bits are from bit 25 to bit 16. So, the * driver needs right shifting by 16. */ - if (mdp->cd->shift_rd0) + if (mdp->cd->hw_crc) desc_status >>= 16; skb = mdp->rx_skbuff[entry]; diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h index 9eec1e185adf..f09fa8b47f9a 100644 --- a/drivers/net/ethernet/renesas/sh_eth.h +++ b/drivers/net/ethernet/renesas/sh_eth.h @@ -490,7 +490,6 @@ struct sh_eth_cpu_data { unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ unsigned hw_crc:1; /* E-DMAC have CSMR */ unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ - unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ unsigned rmiimode:1; /* EtherC has RMIIMODE register */ unsigned rtrate:1; /* EtherC has RTRATE register */ }; |