diff options
author | Sean Wang <sean.wang@mediatek.com> | 2019-06-01 08:03:13 +0800 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2019-06-03 15:00:00 -0700 |
commit | 7093f9d80c7cb82f47628d6477fd4dc252d21a10 (patch) | |
tree | c9214e2966dceed931f27158310006070441ef8f /drivers/net/ethernet/mediatek/mtk_eth_soc.h | |
parent | 9ffee4a8276c734956b8eab19d1c9b0ecb6b79c5 (diff) | |
download | linux-7093f9d80c7cb82f47628d6477fd4dc252d21a10.tar.bz2 |
net: ethernet: mediatek: Integrate hardware path from GMAC to PHY variants
All path route on various SoCs all would be managed in common function
mtk_setup_hw_path that is determined by the both applied devicetree
regarding the path between GMAC and the target PHY or switch by the
capability of target SoC in the runtime.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mediatek/mtk_eth_soc.h')
-rw-r--r-- | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 123 |
1 files changed, 108 insertions, 15 deletions
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 2e65115cf932..89d68dd60b3d 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -373,10 +373,12 @@ #define ETHSYS_SYSCFG0 0x14 #define SYSCFG0_GE_MASK 0x3 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) -#define SYSCFG0_SGMII_MASK (3 << 8) -#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8)) -#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8)) -#define SYSCFG0_SGMII_GMAC2_V2 ((1 << 8) & GENMASK(9, 8)) +#define SYSCFG0_SGMII_MASK GENMASK(9, 8) +#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) +#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) +#define SYSCFG0_SGMII_GMAC1_V2 BIT(9) +#define SYSCFG0_SGMII_GMAC2_V2 BIT(8) + /* ethernet subsystem clock register */ #define ETHSYS_CLKCFG0 0x2c @@ -404,6 +406,11 @@ #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 #define SGMII_PHYA_PWD BIT(4) +/* Infrasys subsystem config registers */ +#define INFRA_MISC2 0x70c +#define CO_QPHY_SEL BIT(0) +#define GEPHY_MAC_SEL BIT(1) + struct mtk_rx_dma { unsigned int rxd1; unsigned int rxd2; @@ -565,19 +572,101 @@ struct mtk_rx_ring { u32 crx_idx_reg; }; -#define MTK_TRGMII BIT(0) -#define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII) -#define MTK_ESW BIT(4) -#define MTK_GMAC1_ESW (BIT(5) | MTK_ESW) -#define MTK_SGMII BIT(8) -#define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII) -#define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII) -#define MTK_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \ - MTK_GMAC2_SGMII) -#define MTK_HWLRO BIT(12) -#define MTK_SHARED_INT BIT(13) +enum mtk_eth_mux { + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW, + MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY, + MTK_ETH_MUX_U3_GMAC2_TO_QPHY, + MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, + MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, + MTK_ETH_MUX_MAX, +}; + +enum mtk_eth_path { + MTK_ETH_PATH_GMAC1_RGMII, + MTK_ETH_PATH_GMAC1_TRGMII, + MTK_ETH_PATH_GMAC1_SGMII, + MTK_ETH_PATH_GMAC2_RGMII, + MTK_ETH_PATH_GMAC2_SGMII, + MTK_ETH_PATH_GMAC2_GEPHY, + MTK_ETH_PATH_GDM1_ESW, + MTK_ETH_PATH_MAX, +}; + +/* Supported hardware group on SoCs */ +#define MTK_RGMII BIT(0) +#define MTK_TRGMII BIT(1) +#define MTK_SGMII BIT(2) +#define MTK_ESW BIT(3) +#define MTK_GEPHY BIT(4) +#define MTK_MUX BIT(5) +#define MTK_INFRA BIT(6) +#define MTK_SHARED_SGMII BIT(7) +#define MTK_HWLRO BIT(8) +#define MTK_SHARED_INT BIT(9) + +/* Supported path present on SoCs */ +#define MTK_PATH_BIT(x) BIT((x) + 10) + +#define MTK_GMAC1_RGMII \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_RGMII) | MTK_RGMII) + +#define MTK_GMAC1_TRGMII \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_TRGMII) | MTK_TRGMII) + +#define MTK_GMAC1_SGMII \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_SGMII) | MTK_SGMII) + +#define MTK_GMAC2_RGMII \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_RGMII) | MTK_RGMII) + +#define MTK_GMAC2_SGMII \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_SGMII) | MTK_SGMII) + +#define MTK_GMAC2_GEPHY \ + (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_GEPHY) | MTK_GEPHY) + +#define MTK_GDM1_ESW \ + (MTK_PATH_BIT(MTK_ETH_PATH_GDM1_ESW) | MTK_ESW) + +#define MTK_MUX_BIT(x) BIT((x) + 20) + +/* MUXes present on SoCs */ +/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ +#define MTK_MUX_GDM1_TO_GMAC1_ESW \ + (MTK_MUX_BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW) | MTK_MUX) + +/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ +#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ + (MTK_MUX_BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY) | MTK_MUX | MTK_INFRA) + +/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ +#define MTK_MUX_U3_GMAC2_TO_QPHY \ + (MTK_MUX_BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY) | MTK_MUX | MTK_INFRA) + +/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ +#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ + (MTK_MUX_BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) | MTK_MUX | \ + MTK_SHARED_SGMII) + +/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ +#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ + (MTK_MUX_BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII) | MTK_MUX) + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) +#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ + MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ + MTK_MUX_GDM1_TO_GMAC1_ESW | \ + MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) + +#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII) + +#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ + MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ + MTK_MUX_U3_GMAC2_TO_QPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII) + /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms * @ana_rgc3: The offset for register ANA_RGC3 related to @@ -633,6 +722,8 @@ struct mtk_sgmii { * @msg_enable: Ethtool msg level * @ethsys: The register map pointing at the range used to setup * MII modes + * @infra: The register map pointing at the range used to setup + * SGMII and GePHY path * @pctl: The register map pointing at the range used to setup * GMAC port drive/slew values * @dma_refcnt: track how many netdevs are using the DMA engine @@ -664,6 +755,7 @@ struct mtk_eth { u32 msg_enable; unsigned long sysclk; struct regmap *ethsys; + struct regmap *infra; struct mtk_sgmii *sgmii; struct regmap *pctl; bool hwlro; @@ -719,5 +811,6 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, u32 ana_rgc3); int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id); +int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode); #endif /* MTK_ETH_H */ |