diff options
| author | Antoine Tenart <antoine.tenart@free-electrons.com> | 2017-10-30 11:23:29 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-11-01 12:28:33 +0900 |
| commit | 7c10f9742d76ec18bed5de14f5f4ed08859f7b7a (patch) | |
| tree | ba5acfe6a6fdb860811b227e691b8a8b2162493c /drivers/net/ethernet/marvell | |
| parent | 2d1d7df8a3652697da7f7929791d555e6c5981c2 (diff) | |
| download | linux-7c10f9742d76ec18bed5de14f5f4ed08859f7b7a.tar.bz2 | |
net: mvpp2: initialize the Tx FIFO size
So far only the Rx FIFO size was initialized. For PPv2.2 the Tx FIFO
size can be set as well. This patch initializes the Tx FIFO size for
PPv2.2 controllers to 3K.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell')
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 2b0ae35d2168..7a6e6ae0a074 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -38,11 +38,12 @@ #include <net/ipv6.h> #include <net/tso.h> -/* RX Fifo Registers */ +/* Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 #define MVPP2_RX_FIFO_INIT_REG 0x64 +#define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) /* RX DMA Top Registers */ #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) @@ -512,6 +513,10 @@ #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 +/* TX FIFO constants */ +#define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa +#define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 + /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) @@ -7811,6 +7816,16 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +/* Initialize Tx FIFO's */ +static void mvpp22_tx_fifo_init(struct mvpp2 *priv) +{ + int port; + + for (port = 0; port < MVPP2_MAX_PORTS; port++) + mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), + MVPP22_TX_FIFO_DATA_SIZE_3KB); +} + static void mvpp2_axi_init(struct mvpp2 *priv) { u32 val, rdval, wrval; @@ -7906,11 +7921,13 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) return err; } - /* Rx Fifo Init */ - if (priv->hw_version == MVPP21) + /* Fifo Init */ + if (priv->hw_version == MVPP21) { mvpp2_rx_fifo_init(priv); - else + } else { mvpp22_rx_fifo_init(priv); + mvpp22_tx_fifo_init(priv); + } if (priv->hw_version == MVPP21) writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, |