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authorJohannes Berg <johannes@sipsolutions.net>2013-07-03 21:48:11 +0200
committerDavid S. Miller <davem@davemloft.net>2013-07-03 16:35:49 -0700
commitbc2bebe8de8ed4ba6482c9cc370b0dd72ffe8cd2 (patch)
tree926f3dffa87c7de6f8f88eaeebe79e81042ecabf /drivers/net/ethernet/atheros/alx/hw.c
parent0c1072ae0242fbdffd9a0bba36e7a7033d287f9c (diff)
downloadlinux-bc2bebe8de8ed4ba6482c9cc370b0dd72ffe8cd2.tar.bz2
alx: remove WoL support
Unfortunately, WoL is broken and the system will immediately resume after suspending, and I can't seem to figure out why. Remove WoL support until the issue can be found. Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/atheros/alx/hw.c')
-rw-r--r--drivers/net/ethernet/atheros/alx/hw.c155
1 files changed, 0 insertions, 155 deletions
diff --git a/drivers/net/ethernet/atheros/alx/hw.c b/drivers/net/ethernet/atheros/alx/hw.c
index ea99e5d8743f..1e8c24a3cb4e 100644
--- a/drivers/net/ethernet/atheros/alx/hw.c
+++ b/drivers/net/ethernet/atheros/alx/hw.c
@@ -332,16 +332,6 @@ void alx_set_macaddr(struct alx_hw *hw, const u8 *addr)
alx_write_mem32(hw, ALX_STAD1, val);
}
-static void alx_enable_osc(struct alx_hw *hw)
-{
- u32 val;
-
- /* rising edge */
- val = alx_read_mem32(hw, ALX_MISC);
- alx_write_mem32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
- alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
-}
-
static void alx_reset_osc(struct alx_hw *hw, u8 rev)
{
u32 val, val2;
@@ -858,66 +848,6 @@ void alx_post_phy_link(struct alx_hw *hw)
}
}
-
-/* NOTE:
- * 1. phy link must be established before calling this function
- * 2. wol option (pattern,magic,link,etc.) is configed before call it.
- */
-int alx_pre_suspend(struct alx_hw *hw, int speed, u8 duplex)
-{
- u32 master, mac, phy, val;
- int err = 0;
-
- master = alx_read_mem32(hw, ALX_MASTER);
- master &= ~ALX_MASTER_PCLKSEL_SRDS;
- mac = hw->rx_ctrl;
- /* 10/100 half */
- ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_10_100);
- mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
-
- phy = alx_read_mem32(hw, ALX_PHY_CTRL);
- phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS);
- phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE |
- ALX_PHY_CTRL_HIB_EN;
-
- /* without any activity */
- if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
- err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
- if (err)
- return err;
- phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN;
- } else {
- if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
- mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN;
- if (hw->sleep_ctrl & ALX_SLEEP_CIFS)
- mac |= ALX_MAC_CTRL_TX_EN;
- if (duplex == DUPLEX_FULL)
- mac |= ALX_MAC_CTRL_FULLD;
- if (speed == SPEED_1000)
- ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,
- ALX_MAC_CTRL_SPEED_1000);
- phy |= ALX_PHY_CTRL_DSPRST_OUT;
- err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
- ALX_MIIEXT_S3DIG10,
- ALX_MIIEXT_S3DIG10_SL);
- if (err)
- return err;
- }
-
- alx_enable_osc(hw);
- hw->rx_ctrl = mac;
- alx_write_mem32(hw, ALX_MASTER, master);
- alx_write_mem32(hw, ALX_MAC_CTRL, mac);
- alx_write_mem32(hw, ALX_PHY_CTRL, phy);
-
- /* set val of PDLL D3PLLOFF */
- val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
- val |= ALX_PDLL_TRNS1_D3PLLOFF_EN;
- alx_write_mem32(hw, ALX_PDLL_TRNS1, val);
-
- return 0;
-}
-
bool alx_phy_configured(struct alx_hw *hw)
{
u32 cfg, hw_cfg;
@@ -990,26 +920,6 @@ int alx_clear_phy_intr(struct alx_hw *hw)
return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
}
-int alx_config_wol(struct alx_hw *hw)
-{
- u32 wol = 0;
- int err = 0;
-
- /* turn on magic packet event */
- if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
- wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN;
-
- /* turn on link up event */
- if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
- wol |= ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK;
- /* only link up can wake up */
- err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
- }
- alx_write_mem32(hw, ALX_WOL0, wol);
-
- return err;
-}
-
void alx_disable_rss(struct alx_hw *hw)
{
u32 ctrl = alx_read_mem32(hw, ALX_RXQ0);
@@ -1121,71 +1031,6 @@ void alx_configure_basic(struct alx_hw *hw)
alx_write_mem32(hw, ALX_WRR, val);
}
-int alx_select_powersaving_speed(struct alx_hw *hw, int *speed, u8 *duplex)
-{
- int i, err;
- u16 lpa;
-
- err = alx_read_phy_link(hw);
- if (err)
- return err;
-
- if (hw->link_speed == SPEED_UNKNOWN) {
- *speed = SPEED_UNKNOWN;
- *duplex = DUPLEX_UNKNOWN;
- return 0;
- }
-
- err = alx_read_phy_reg(hw, MII_LPA, &lpa);
- if (err)
- return err;
-
- if (!(lpa & LPA_LPACK)) {
- *speed = hw->link_speed;
- return 0;
- }
-
- if (lpa & LPA_10FULL) {
- *speed = SPEED_10;
- *duplex = DUPLEX_FULL;
- } else if (lpa & LPA_10HALF) {
- *speed = SPEED_10;
- *duplex = DUPLEX_HALF;
- } else if (lpa & LPA_100FULL) {
- *speed = SPEED_100;
- *duplex = DUPLEX_FULL;
- } else {
- *speed = SPEED_100;
- *duplex = DUPLEX_HALF;
- }
-
- if (*speed == hw->link_speed && *duplex == hw->duplex)
- return 0;
- err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
- if (err)
- return err;
- err = alx_setup_speed_duplex(hw, alx_speed_to_ethadv(*speed, *duplex) |
- ADVERTISED_Autoneg, ALX_FC_ANEG |
- ALX_FC_RX | ALX_FC_TX);
- if (err)
- return err;
-
- /* wait for linkup */
- for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
- msleep(100);
-
- err = alx_read_phy_link(hw);
- if (err < 0)
- return err;
- if (hw->link_speed != SPEED_UNKNOWN)
- break;
- }
- if (i == ALX_MAX_SETUP_LNK_CYCLE)
- return -ETIMEDOUT;
-
- return 0;
-}
-
bool alx_get_phy_info(struct alx_hw *hw)
{
u16 devs1, devs2;