diff options
author | Mike Frysinger <vapier@gentoo.org> | 2011-06-24 04:33:02 +0000 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-06-27 20:42:24 -0700 |
commit | cfbf7586bc07cd6d14cd93ca56d8a3f90e248625 (patch) | |
tree | 16418209e4bea1c9c54ada013867f46f3d6295e6 /drivers/net/can | |
parent | 9118f08a7794e9a4908afbb0f9bc9455325a5631 (diff) | |
download | linux-cfbf7586bc07cd6d14cd93ca56d8a3f90e248625.tar.bz2 |
can: bfin_can: auto-calculate accessor sizes
Since we have a struct that defines the sizes of the registers, we don't
need to explicitly use the 16bit read/write helpers. Let the code figure
out which size access to make based on the size of the C type.
There should be no functional changes here.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/can')
-rw-r--r-- | drivers/net/can/bfin_can.c | 118 |
1 files changed, 59 insertions, 59 deletions
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c index dc6ef4a9e02a..a1c5abc38cd2 100644 --- a/drivers/net/can/bfin_can.c +++ b/drivers/net/can/bfin_can.c @@ -79,8 +79,8 @@ static int bfin_can_set_bittiming(struct net_device *dev) if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) timing |= SAM; - bfin_write16(®->clock, clk); - bfin_write16(®->timing, timing); + bfin_write(®->clock, clk); + bfin_write(®->timing, timing); dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); @@ -96,16 +96,16 @@ static void bfin_can_set_reset_mode(struct net_device *dev) int i; /* disable interrupts */ - bfin_write16(®->mbim1, 0); - bfin_write16(®->mbim2, 0); - bfin_write16(®->gim, 0); + bfin_write(®->mbim1, 0); + bfin_write(®->mbim2, 0); + bfin_write(®->gim, 0); /* reset can and enter configuration mode */ - bfin_write16(®->control, SRS | CCR); + bfin_write(®->control, SRS | CCR); SSYNC(); - bfin_write16(®->control, CCR); + bfin_write(®->control, CCR); SSYNC(); - while (!(bfin_read16(®->control) & CCA)) { + while (!(bfin_read(®->control) & CCA)) { udelay(10); if (--timeout == 0) { dev_err(dev->dev.parent, @@ -119,33 +119,33 @@ static void bfin_can_set_reset_mode(struct net_device *dev) * by writing to CAN Mailbox Configuration Registers 1 and 2 * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled */ - bfin_write16(®->mc1, 0); - bfin_write16(®->mc2, 0); + bfin_write(®->mc1, 0); + bfin_write(®->mc2, 0); /* Set Mailbox Direction */ - bfin_write16(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ - bfin_write16(®->md2, 0); /* mailbox 17-32 are TX */ + bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ + bfin_write(®->md2, 0); /* mailbox 17-32 are TX */ /* RECEIVE_STD_CHL */ for (i = 0; i < 2; i++) { - bfin_write16(®->chl[RECEIVE_STD_CHL + i].id0, 0); - bfin_write16(®->chl[RECEIVE_STD_CHL + i].id1, AME); - bfin_write16(®->chl[RECEIVE_STD_CHL + i].dlc, 0); - bfin_write16(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); - bfin_write16(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); + bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0); + bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME); + bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0); + bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); + bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); } /* RECEIVE_EXT_CHL */ for (i = 0; i < 2; i++) { - bfin_write16(®->chl[RECEIVE_EXT_CHL + i].id0, 0); - bfin_write16(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); - bfin_write16(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); - bfin_write16(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); - bfin_write16(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); + bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0); + bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); + bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); + bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); + bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); } - bfin_write16(®->mc2, BIT(TRANSMIT_CHL - 16)); - bfin_write16(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); + bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16)); + bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); SSYNC(); priv->can.state = CAN_STATE_STOPPED; @@ -160,9 +160,9 @@ static void bfin_can_set_normal_mode(struct net_device *dev) /* * leave configuration mode */ - bfin_write16(®->control, bfin_read16(®->control) & ~CCR); + bfin_write(®->control, bfin_read(®->control) & ~CCR); - while (bfin_read16(®->status) & CCA) { + while (bfin_read(®->status) & CCA) { udelay(10); if (--timeout == 0) { dev_err(dev->dev.parent, @@ -174,25 +174,25 @@ static void bfin_can_set_normal_mode(struct net_device *dev) /* * clear _All_ tx and rx interrupts */ - bfin_write16(®->mbtif1, 0xFFFF); - bfin_write16(®->mbtif2, 0xFFFF); - bfin_write16(®->mbrif1, 0xFFFF); - bfin_write16(®->mbrif2, 0xFFFF); + bfin_write(®->mbtif1, 0xFFFF); + bfin_write(®->mbtif2, 0xFFFF); + bfin_write(®->mbrif1, 0xFFFF); + bfin_write(®->mbrif2, 0xFFFF); /* * clear global interrupt status register */ - bfin_write16(®->gis, 0x7FF); /* overwrites with '1' */ + bfin_write(®->gis, 0x7FF); /* overwrites with '1' */ /* * Initialize Interrupts * - set bits in the mailbox interrupt mask register * - global interrupt mask */ - bfin_write16(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); - bfin_write16(®->mbim2, BIT(TRANSMIT_CHL - 16)); + bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); + bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16)); - bfin_write16(®->gim, EPIM | BOIM | RMLIM); + bfin_write(®->gim, EPIM | BOIM | RMLIM); SSYNC(); } @@ -242,28 +242,28 @@ static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev) /* fill id */ if (id & CAN_EFF_FLAG) { - bfin_write16(®->chl[TRANSMIT_CHL].id0, id); + bfin_write(®->chl[TRANSMIT_CHL].id0, id); val = ((id & 0x1FFF0000) >> 16) | IDE; } else val = (id << 2); if (id & CAN_RTR_FLAG) val |= RTR; - bfin_write16(®->chl[TRANSMIT_CHL].id1, val | AME); + bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME); /* fill payload */ for (i = 0; i < 8; i += 2) { val = ((7 - i) < dlc ? (data[7 - i]) : 0) + ((6 - i) < dlc ? (data[6 - i] << 8) : 0); - bfin_write16(®->chl[TRANSMIT_CHL].data[i], val); + bfin_write(®->chl[TRANSMIT_CHL].data[i], val); } /* fill data length code */ - bfin_write16(®->chl[TRANSMIT_CHL].dlc, dlc); + bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc); can_put_echo_skb(skb, dev, 0); /* set transmit request */ - bfin_write16(®->trs2, BIT(TRANSMIT_CHL - 16)); + bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16)); return 0; } @@ -286,26 +286,26 @@ static void bfin_can_rx(struct net_device *dev, u16 isrc) /* get id */ if (isrc & BIT(RECEIVE_EXT_CHL)) { /* extended frame format (EFF) */ - cf->can_id = ((bfin_read16(®->chl[RECEIVE_EXT_CHL].id1) + cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1) & 0x1FFF) << 16) - + bfin_read16(®->chl[RECEIVE_EXT_CHL].id0); + + bfin_read(®->chl[RECEIVE_EXT_CHL].id0); cf->can_id |= CAN_EFF_FLAG; obj = RECEIVE_EXT_CHL; } else { /* standard frame format (SFF) */ - cf->can_id = (bfin_read16(®->chl[RECEIVE_STD_CHL].id1) + cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1) & 0x1ffc) >> 2; obj = RECEIVE_STD_CHL; } - if (bfin_read16(®->chl[obj].id1) & RTR) + if (bfin_read(®->chl[obj].id1) & RTR) cf->can_id |= CAN_RTR_FLAG; /* get data length code */ - cf->can_dlc = get_can_dlc(bfin_read16(®->chl[obj].dlc) & 0xF); + cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF); /* get payload */ for (i = 0; i < 8; i += 2) { - val = bfin_read16(®->chl[obj].data[i]); + val = bfin_read(®->chl[obj].data[i]); cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; } @@ -359,7 +359,7 @@ static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || state == CAN_STATE_ERROR_PASSIVE)) { - u16 cec = bfin_read16(®->cec); + u16 cec = bfin_read(®->cec); u8 rxerr = cec; u8 txerr = cec >> 8; @@ -410,23 +410,23 @@ irqreturn_t bfin_can_interrupt(int irq, void *dev_id) struct net_device_stats *stats = &dev->stats; u16 status, isrc; - if ((irq == priv->tx_irq) && bfin_read16(®->mbtif2)) { + if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) { /* transmission complete interrupt */ - bfin_write16(®->mbtif2, 0xFFFF); + bfin_write(®->mbtif2, 0xFFFF); stats->tx_packets++; - stats->tx_bytes += bfin_read16(®->chl[TRANSMIT_CHL].dlc); + stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc); can_get_echo_skb(dev, 0); netif_wake_queue(dev); - } else if ((irq == priv->rx_irq) && bfin_read16(®->mbrif1)) { + } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) { /* receive interrupt */ - isrc = bfin_read16(®->mbrif1); - bfin_write16(®->mbrif1, 0xFFFF); + isrc = bfin_read(®->mbrif1); + bfin_write(®->mbrif1, 0xFFFF); bfin_can_rx(dev, isrc); - } else if ((irq == priv->err_irq) && bfin_read16(®->gis)) { + } else if ((irq == priv->err_irq) && bfin_read(®->gis)) { /* error interrupt */ - isrc = bfin_read16(®->gis); - status = bfin_read16(®->esr); - bfin_write16(®->gis, 0x7FF); + isrc = bfin_read(®->gis); + status = bfin_read(®->esr); + bfin_write(®->gis, 0x7FF); bfin_can_err(dev, isrc, status); } else { return IRQ_NONE; @@ -631,9 +631,9 @@ static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg) if (netif_running(dev)) { /* enter sleep mode */ - bfin_write16(®->control, bfin_read16(®->control) | SMR); + bfin_write(®->control, bfin_read(®->control) | SMR); SSYNC(); - while (!(bfin_read16(®->intr) & SMACK)) { + while (!(bfin_read(®->intr) & SMACK)) { udelay(10); if (--timeout == 0) { dev_err(dev->dev.parent, @@ -654,7 +654,7 @@ static int bfin_can_resume(struct platform_device *pdev) if (netif_running(dev)) { /* leave sleep mode */ - bfin_write16(®->intr, 0); + bfin_write(®->intr, 0); SSYNC(); } |