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| author | Thierry Reding <treding@nvidia.com> | 2019-10-16 13:50:26 +0200 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-10-18 11:46:11 +0200 |
| commit | 96d3ab802e4930a29a33934373157d6dff1b2c7e (patch) | |
| tree | 865c8369b01a79df48785d07c22a164c91ff2092 /drivers/net/can/xilinx_can.c | |
| parent | e31e5929547edf396ea2c0873244c734c6bceafa (diff) | |
| download | linux-96d3ab802e4930a29a33934373157d6dff1b2c7e.tar.bz2 | |
iommu/tegra-smmu: Fix page tables in > 4 GiB memory
Page tables that reside in physical memory beyond the 4 GiB boundary are
currently not working properly. The reason is that when the physical
address for page directory entries is read, it gets truncated at 32 bits
and can cause crashes when passing that address to the DMA API.
Fix this by first casting the PDE value to a dma_addr_t and then using
the page frame number mask for the SMMU instance to mask out the invalid
bits, which are typically used for mapping attributes, etc.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/net/can/xilinx_can.c')
0 files changed, 0 insertions, 0 deletions