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authorMarc Kleine-Budde <mkl@pengutronix.de>2019-03-01 10:22:26 +0100
committerMarc Kleine-Budde <mkl@pengutronix.de>2019-11-11 21:58:11 +0100
commit9ed63c60c9e3ace16e4307866cc01e8ddf296155 (patch)
tree40c8cfc0d74c7f327b6fdb5d68589d3b8956c3e3 /drivers/net/can/flexcan.c
parent07c054d3e53fe27025dae5e232465c8ecf658ebf (diff)
downloadlinux-9ed63c60c9e3ace16e4307866cc01e8ddf296155.tar.bz2
can: flexcan: remove TX mailbox bit from struct flexcan_priv::rx_mask{1,2}
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of struct flexcan_priv for this. Currently these values cannot be used directly, as they contain the TX mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1 and flexcan_priv::rx_mask2, and sets the TX flag directly when writing the regs->iflag1 and regs->iflag2 into the hardware. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net/can/flexcan.c')
-rw-r--r--drivers/net/can/flexcan.c14
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 44ac211af7eb..29d1dbe89351 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -878,8 +878,7 @@ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
struct flexcan_regs __iomem *regs = priv->regs;
u32 iflag1, iflag2;
- iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2 &
- ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
+ iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2;
iflag1 = priv->read(&regs->iflag1) & priv->rx_mask1;
return (u64)iflag2 << 32 | iflag1;
@@ -1228,7 +1227,7 @@ static int flexcan_chip_start(struct net_device *dev)
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, &regs->ctrl);
priv->write(priv->rx_mask1, &regs->imask1);
- priv->write(priv->rx_mask2, &regs->imask2);
+ priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), &regs->imask2);
enable_irq(dev->irq);
/* print chip status */
@@ -1297,9 +1296,6 @@ static int flexcan_open(struct net_device *dev)
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
- priv->rx_mask1 = 0;
- priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
-
priv->offload.mailbox_read = flexcan_mailbox_read;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
@@ -1310,12 +1306,12 @@ static int flexcan_open(struct net_device *dev)
imask = GENMASK_ULL(priv->offload.mb_last,
priv->offload.mb_first);
- priv->rx_mask1 |= imask;
- priv->rx_mask2 |= imask >> 32;
+ priv->rx_mask1 = imask;
+ priv->rx_mask2 = imask >> 32;
err = can_rx_offload_add_timestamp(dev, &priv->offload);
} else {
- priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+ priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
err = can_rx_offload_add_fifo(dev, &priv->offload,
FLEXCAN_NAPI_WEIGHT);