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authorFrank Li <Frank.Li@freescale.com>2015-08-04 10:25:35 -0500
committerBrian Norris <computersforpeace@gmail.com>2015-08-06 10:07:40 -0700
commitd371cbfc151c6a7229150da0954d1f74ea4dcd39 (patch)
tree7ed194d52c7c48adbdfd18bc0127287b99f4f7db /drivers/mtd
parent80d37724089bc5d09fa12601a763bde01899ba88 (diff)
downloadlinux-d371cbfc151c6a7229150da0954d1f74ea4dcd39.tar.bz2
mtd: spi-nor: fsl-quadspi: add imx7d support
Support i.mx7d. quadspi in i.mx7d increase rxfifo. require fill at least 16byte to trigger data transfer. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Han Xu <han.xu@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/spi-nor/fsl-quadspi.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 91bfeac79722..b567756b4cc2 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -32,6 +32,11 @@
#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
/* Controller needs 4x internal clock */
#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
+/*
+ * TKT253890, Controller needs driver to fill txfifo till 16 byte to
+ * trigger data transfer even though extern data will not transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890 (1 << 2)
/* The registers */
#define QUADSPI_MCR 0x00
@@ -202,6 +207,7 @@
enum fsl_qspi_devtype {
FSL_QUADSPI_VYBRID,
FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX7D,
};
struct fsl_qspi_devtype_data {
@@ -228,6 +234,15 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
.driver_data = QUADSPI_QUIRK_4X_INT_CLK,
};
+static struct fsl_qspi_devtype_data imx7d_data = {
+ .devtype = FSL_QUADSPI_IMX7D,
+ .rxfifo = 512,
+ .txfifo = 512,
+ .ahb_buf_size = 1024,
+ .driver_data = QUADSPI_QUIRK_TKT253890
+ | QUADSPI_QUIRK_4X_INT_CLK,
+};
+
#define FSL_QSPI_MAX_CHIP 4
struct fsl_qspi {
struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
@@ -259,6 +274,11 @@ static inline int needs_4x_clock(struct fsl_qspi *q)
return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
}
+static inline int needs_fill_txfifo(struct fsl_qspi *q)
+{
+ return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
+}
+
/*
* An IC bug makes us to re-arrange the 32-bit data.
* The following chips, such as IMX6SLX, have fixed this bug.
@@ -560,6 +580,11 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
txbuf++;
}
+ /* fill the TXFIFO upto 16 bytes for i.MX7d */
+ if (needs_fill_txfifo(q))
+ for (; i < 4; i++)
+ writel(tmp, q->iobase + QUADSPI_TBDR);
+
/* Trigger it */
ret = fsl_qspi_runcmd(q, opcode, to, count);
@@ -679,6 +704,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
+ { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);