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authorMike Dunn <mikedunn@newsguy.com>2012-03-11 14:21:11 -0700
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-03-27 00:56:46 +0100
commit6a918bade9dab40aaef80559bd1169c69e8d69cb (patch)
tree1be69789f9b6c6e064a36f4ef6e142a8ec0058b5 /drivers/mtd/nand/sh_flctl.c
parent1d0b95b0834087ba3653f69c24483d63a26d51a7 (diff)
downloadlinux-6a918bade9dab40aaef80559bd1169c69e8d69cb.tar.bz2
mtd: flash drivers set ecc strength
Flash device drivers initialize 'ecc_strength' in struct mtd_info, which is the maximum number of bit errors that can be corrected in one writesize region. Drivers using the nand interface intitialize 'strength' in struct nand_ecc_ctrl, which is the maximum number of bit errors that can be corrected in one ecc step. Nand infrastructure code translates this to 'ecc_strength'. Also for nand drivers, the nand infrastructure code sets ecc.strength for ecc modes NAND_ECC_SOFT, NAND_ECC_SOFT_BCH, and NAND_ECC_NONE. It is set in the driver for all other modes. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/sh_flctl.c')
-rw-r--r--drivers/mtd/nand/sh_flctl.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 2ee9a1b50a22..e9b2b260de3a 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -825,6 +825,7 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
chip->ecc.size = 512;
chip->ecc.bytes = 10;
+ chip->ecc.strength = 4;
chip->ecc.read_page = flctl_read_page_hwecc;
chip->ecc.write_page = flctl_write_page_hwecc;
chip->ecc.mode = NAND_ECC_HW;