diff options
| author | Javier Martin <javier.martin@vista-silicon.com> | 2012-05-11 12:15:41 +0200 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-05-13 23:33:05 -0500 |
| commit | 43dc03c7ba644620283523b7ae62da94bb81fdbb (patch) | |
| tree | 4667af816f014fe508fd7031e7393adc9a153dc9 /drivers/mtd/chips | |
| parent | 8c5a0366403f5dbca9d4ccf50f95bafbaddc2844 (diff) | |
| download | linux-43dc03c7ba644620283523b7ae62da94bb81fdbb.tar.bz2 | |
mtd: add fixup for S29NS512P NOR flash.
Spansion S29NS512P flash uses a 16bit transfer to report number
of sectors instead of two 8bit accesses as CFI specifies.
Artem: remove warning message which said that we are applying the
fixup - no need to scary the user unnecessarily.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/chips')
| -rw-r--r-- | drivers/mtd/chips/cfi_cmdset_0002.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index d02592e6a0f0..49b8b035e8e1 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -332,6 +332,19 @@ static void fixup_s29gl032n_sectors(struct mtd_info *mtd) } } +static void fixup_s29ns512p_sectors(struct mtd_info *mtd) +{ + struct map_info *map = mtd->priv; + struct cfi_private *cfi = map->fldrv_priv; + + /* + * S29NS512P flash uses more than 8bits to report number of sectors, + * which is not permitted by CFI. + */ + cfi->cfiq->EraseRegionInfo[0] = 0x020001ff; + pr_warning("%s: Bad S29NS512P CFI data, adjust to 512 sectors\n", mtd->name); +} + /* Used to fix CFI-Tables of chips without Extended Query Tables */ static struct cfi_fixup cfi_nopri_fixup_table[] = { { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */ @@ -362,6 +375,7 @@ static struct cfi_fixup cfi_fixup_table[] = { { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors }, { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors }, { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors }, + { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors }, { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */ { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */ { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */ |