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authorAdrian Hunter <adrian.hunter@intel.com>2018-02-14 15:57:44 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2018-03-05 13:04:31 +0100
commit7b7d57fd1b773d25d8358c6017592b4928bf76ce (patch)
treef2e67304c95deed69c4d055993fe5c9211f956e3 /drivers/mmc
parent129d21ce15af027696864b2798b41f4514f1c8c2 (diff)
downloadlinux-7b7d57fd1b773d25d8358c6017592b4928bf76ce.tar.bz2
mmc: sdhci-pci: Get rid of glk_cqe_enable()
Now that tuning no longer leaves the Buffer Read Enable bit set (refer intel_execute_tuning()), glk_cqe_enable() is no longer needed. Get rid of it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-pci-core.c20
1 files changed, 1 insertions, 19 deletions
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index 82c4f05f91d8..ce21d86a8141 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -712,26 +712,8 @@ static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
return ret;
}
-static void glk_cqe_enable(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- u32 reg;
-
- /*
- * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
- * the case after tuning, so ensure the buffer is drained.
- */
- reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
- while (reg & SDHCI_DATA_AVAILABLE) {
- sdhci_readl(host, SDHCI_BUFFER);
- reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
- }
-
- sdhci_cqe_enable(mmc);
-}
-
static const struct cqhci_host_ops glk_cqhci_ops = {
- .enable = glk_cqe_enable,
+ .enable = sdhci_cqe_enable,
.disable = sdhci_cqe_disable,
.dumpregs = sdhci_pci_dumpregs,
};