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authorAndrew Bresticker <abrestic@chromium.org>2014-05-22 08:55:36 -0700
committerChris Ball <chris@printf.net>2014-05-23 08:49:29 -0400
commitf92603552dbf9c10c5c1d557eec80226d3effdb9 (patch)
tree2a6aa88eb26d444adb53ea01e854bb70f92bc0e4 /drivers/mmc
parent3145351a6f4026fa9e9f8c7a0ba85a877377e0e3 (diff)
downloadlinux-f92603552dbf9c10c5c1d557eec80226d3effdb9.tar.bz2
mmc: tegra: fix reporting of base clock frequency
Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. This is because the clock rate is configured by the clock controller, which is external to the SD/MMC controller. Since the SD/MMC controller has no knowledge of how this clock is configured, it will simply report the maximum frequency. While the reported value can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN and supply sdhci_pltfm_clk_get_max_clock(), which simply does a clk_get_rate(), as the get_max_clock() callback. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-tegra.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 4375cd4704c6..d93a063a36f3 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -154,13 +154,15 @@ static const struct sdhci_ops tegra_sdhci_ops = {
.set_bus_width = tegra_sdhci_set_bus_width,
.reset = tegra_sdhci_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
};
static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_NO_HISPD_BIT |
- SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
+ SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.ops = &tegra_sdhci_ops,
};
@@ -175,7 +177,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_NO_HISPD_BIT |
- SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
+ SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.ops = &tegra_sdhci_ops,
};
@@ -191,7 +194,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_NO_HISPD_BIT |
- SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
+ SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.ops = &tegra_sdhci_ops,
};