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authorOded Gabbay <oded.gabbay@gmail.com>2019-05-29 17:30:04 +0300
committerOded Gabbay <oded.gabbay@gmail.com>2019-05-29 17:30:04 +0300
commit95b5a8b83e06ccc44feff2c0cfb1881468596e7c (patch)
tree5c5ad04bba49e3abcbd384c1c13395912e07edaf /drivers/misc/habanalabs/debugfs.c
parent7aa2227affb510c609954000943e4bdce06d112c (diff)
downloadlinux-95b5a8b83e06ccc44feff2c0cfb1881468596e7c.tar.bz2
habanalabs: add MMU mappings for Goya CPU
This patch adds the necessary MMU mappings for the Goya CPU to access the device DRAM and the host memory. The first 256MB of the device DRAM is being mapped. That's where the F/W is running. The 2MB area located on the host memory for the purpose of communication between the driver and the device CPU is also being mapped. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat (limited to 'drivers/misc/habanalabs/debugfs.c')
-rw-r--r--drivers/misc/habanalabs/debugfs.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/misc/habanalabs/debugfs.c b/drivers/misc/habanalabs/debugfs.c
index ba418aaa404c..886f8ea82499 100644
--- a/drivers/misc/habanalabs/debugfs.c
+++ b/drivers/misc/habanalabs/debugfs.c
@@ -355,7 +355,7 @@ static int mmu_show(struct seq_file *s, void *data)
struct hl_debugfs_entry *entry = s->private;
struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
struct hl_device *hdev = dev_entry->hdev;
- struct hl_ctx *ctx = hdev->user_ctx;
+ struct hl_ctx *ctx;
u64 hop0_addr = 0, hop0_pte_addr = 0, hop0_pte = 0,
hop1_addr = 0, hop1_pte_addr = 0, hop1_pte = 0,
@@ -367,6 +367,11 @@ static int mmu_show(struct seq_file *s, void *data)
if (!hdev->mmu_enable)
return 0;
+ if (dev_entry->mmu_asid == HL_KERNEL_ASID_ID)
+ ctx = hdev->kernel_ctx;
+ else
+ ctx = hdev->user_ctx;
+
if (!ctx) {
dev_err(hdev->dev, "no ctx available\n");
return 0;