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authorMicky Ching <micky_ching@realsil.com.cn>2015-02-25 13:50:13 +0800
committerLee Jones <lee.jones@linaro.org>2015-03-03 16:41:19 +0000
commit19f3bd548f2750a8a7e4e6d2f25fdc5f8e2c3ee9 (patch)
tree6eeb54b69860e8150f5a46cca024778198a973c5 /drivers/mfd/rts5249.c
parentb038538104d5b033d3beaffba6d6efe01246930b (diff)
downloadlinux-19f3bd548f2750a8a7e4e6d2f25fdc5f8e2c3ee9.tar.bz2
mfd: rtsx: Remove LCTLR defination
To enable/disable ASPM we should find LINK CONTROL register in PCI config space. All old chip use 0x80 address, but new chip may use another address, so we using pci_find_capability() to get LINK CONTROL address. rtsx_gops.c was removed, we consider to put some common operations to this file, but the actual thing is, only a group of chips are in common ops1, and another group of chips in common ops2, it is hard to decide put which ops into generic ops file. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/rts5249.c')
-rw-r--r--drivers/mfd/rts5249.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 8de822048ff2..3c77058a70d2 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -119,7 +119,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
else
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
- rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
return rtsx_pci_send_cmd(pcr, 100);
}
@@ -128,7 +127,7 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
{
int err;
- err = rtsx_gops_pm_reset(pcr);
+ err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
if (err < 0)
return err;