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author | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-05-04 10:08:10 -0400 |
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committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-05-17 06:22:08 -0400 |
commit | 6f684d4fcce5eddd7e216a18975fb798d11a83dd (patch) | |
tree | eaff79642c38ec032dc6d550d5daafc8f3be2654 /drivers/media/platform/vsp1/vsp1_entity.h | |
parent | 28d42d2fcaad68fa81a328adfb027323796e5f6e (diff) | |
download | linux-6f684d4fcce5eddd7e216a18975fb798d11a83dd.tar.bz2 |
media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver
The Cadence MIPI-CSI2 TX controller is an hardware block meant to be used
as a bridge between pixel interfaces and a CSI-2 bus.
It supports operating with an internal or external D-PHY, with up to 4
lanes, or without any D-PHY. The current code only supports the latter
case.
While the virtual channel input on the pixel interface can be directly
mapped to CSI2, the datatype input is actually a selection signal (3-bits)
mapping to a table of up to 8 preconfigured datatypes/formats (programmed
at start-up)
The block supports up to 8 input datatypes.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media/platform/vsp1/vsp1_entity.h')
0 files changed, 0 insertions, 0 deletions