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| author | Peter Senna Tschudin <peter.senna@gmail.com> | 2012-06-14 13:58:16 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-06-21 18:01:54 -0300 |
| commit | 3f7c0a69ab1181a0f5e4ead5d4b270d404c6465c (patch) | |
| tree | 266e02f68825068bf8da182b2c35009a282f4433 /drivers/media/dvb/frontends | |
| parent | 59f6a93fae656409042c8a55e8b9088893c40378 (diff) | |
| download | linux-3f7c0a69ab1181a0f5e4ead5d4b270d404c6465c.tar.bz2 | |
[media] s5h1420: Unused variable clock_setting
The switch/case was setting clock_setting that is not being used. Both switch/case and the variable definition were removed.
Currently clock is being calculated by the formula:
(state->fclk/1000000 - 8)
Tested by compilation only.
Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends')
| -rw-r--r-- | drivers/media/dvb/frontends/s5h1420.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/media/dvb/frontends/s5h1420.c b/drivers/media/dvb/frontends/s5h1420.c index 2322257c69ae..e2fec9ebf947 100644 --- a/drivers/media/dvb/frontends/s5h1420.c +++ b/drivers/media/dvb/frontends/s5h1420.c @@ -634,7 +634,6 @@ static int s5h1420_set_frontend(struct dvb_frontend *fe) struct s5h1420_state* state = fe->demodulator_priv; int frequency_delta; struct dvb_frontend_tune_settings fesettings; - uint8_t clock_setting; dprintk("enter %s\n", __func__); @@ -679,25 +678,6 @@ static int s5h1420_set_frontend(struct dvb_frontend *fe) else state->fclk = 44000000; - /* Clock */ - switch (state->fclk) { - default: - case 88000000: - clock_setting = 80; - break; - case 86000000: - clock_setting = 78; - break; - case 80000000: - clock_setting = 72; - break; - case 59000000: - clock_setting = 51; - break; - case 44000000: - clock_setting = 36; - break; - } dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); s5h1420_writereg(state, PLL02, 0x40); |