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authorStefan Popa <stefan.popa@analog.com>2019-06-04 17:58:02 +0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-06-17 21:06:45 +0100
commit7f699bd14913423ce971f7b8d725448093eaa51a (patch)
treee0df1f9d56986f7259de6ae1c9ac6467c2bf3a2c /drivers/macintosh/ans-lcd.h
parent81956a93b552205b35250f19120058fc3337e01e (diff)
downloadlinux-7f699bd14913423ce971f7b8d725448093eaa51a.tar.bz2
iio: frequency: adf4371: Add support for ADF4371 PLL
The ADF4371 is a frequency synthesizer with an integrated voltage controlled oscillator (VCO) for phase-locked loops (PLLs). The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. The driver takes the reference input frequency from the device tree and uses it to calculate and maximize the PFD frequency (frequency of the phase frequency detector). The PFD frequency is further used to calculate the timeouts: synthesizer lock, VCO band selection, automatic level calibration (ALC) and PLL settling time. This initial driver exposes the attributes for setting the frequency and enabling/disabling the different adf4371 channels. Datasheet: Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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