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authorStephen Boyd <sboyd@codeaurora.org>2017-08-23 15:31:48 -0700
committerStephen Boyd <sboyd@codeaurora.org>2017-08-23 15:31:48 -0700
commit1fea70bc1839ac60a89f4b5d50e2b3e160aa74e2 (patch)
tree18deff41fc5a8874dd2ab25cc6a871f2681878c0 /drivers/irqchip
parent4d64556b3622166216db754211858447079e7c96 (diff)
parentcd030a78f7aa06fe216f6665a6ea84b8f3e5b3d3 (diff)
downloadlinux-1fea70bc1839ac60a89f4b5d50e2b3e160aa74e2.tar.bz2
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock changes from Chen-Yu Tsai: * Added support for fixed post-divider on divider and NKM-style clocks * Added driver for R40 CCU * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo * Make fractional clock modes really used and correctly configured * Make H3 cpu clock rate change correctly to be used with cpufreq * tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: support R40 SoC dt-bindings: add compatible string for Allwinner R40 CCU clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: div: Add support for fixed post-divider dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Wait for lock when using fractional mode clk: sunxi-ng: Make fractional helper less chatty clk: sunxi-ng: multiplier: Fix fractional mode clk: sunxi-ng: Fix fractional mode for N-M clocks clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
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