diff options
author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:27 -0700 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-29 15:21:57 +0200 |
commit | 93c5bba575cedbeb50c9e1b0676230139b0d1be1 (patch) | |
tree | 36867c2819d5076b8c99da2b365d1d4c2d3a8f8a /drivers/irqchip/irq-mips-gic.c | |
parent | b025d51873d5fe6f05f8e94174282cb00ef1f489 (diff) | |
download | linux-93c5bba575cedbeb50c9e1b0676230139b0d1be1.tar.bz2 |
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts
There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h
when declaring macros corresponding to register fields. This patch
modifies our definitions to do so.
The *_SHF definitions are removed entirely - they duplicate information
found in the masks, are infrequently used & can be replaced with use of
__ffs() where needed.
The *_MSK definitions then lose their _MSK suffix which is now somewhat
redundant, and users are modified to match.
The field definitions are moved to follow the appropriate register's
accessor functions, which helps to keep the field definitions in order &
to find the appropriate fields for a given register. Whilst here a
comment is added describing each register & including its name, which is
helpful both for linking the register back to hardware documentation &
for grepping purposes.
This also cleans up a couple of issues that became obvious as a result
of making the changes described above:
- We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony
copy of that named GCR_RESET_EXT_BASE - a register which does not
exist. The bad definitions were added by commit 497e803ebf98 ("MIPS:
smp-cps: Ensure secondary cores start with EVA disabled") and made
use of from boot_core(), which is now modified to use the
GCR_Cx_RESET_EXT_BASE definitions.
- We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly
define this as inFo rather than inGo.
Now that we don't duplicate field information between _SHF & _MSK
definitions, and keep the fields next to the register accessors, it will
be much easier to spot & prevent any similar oddities being introduced
in the future.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17001/
Patchwork: https://patchwork.linux-mips.org/patch/17216/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/irqchip/irq-mips-gic.c')
-rw-r--r-- | drivers/irqchip/irq-mips-gic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 6ab1d3afec02..ae9f8e581d06 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -1009,7 +1009,7 @@ static int __init gic_of_init(struct device_node *node, */ if (mips_cm_present()) { gic_base = read_gcr_gic_base() & - ~CM_GCR_GIC_BASE_GICEN_MSK; + ~CM_GCR_GIC_BASE_GICEN; gic_len = 0x20000; } else { pr_err("Failed to get GIC memory range\n"); @@ -1021,7 +1021,7 @@ static int __init gic_of_init(struct device_node *node, } if (mips_cm_present()) - write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); + write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); gic_present = true; __gic_init(gic_base, gic_len, cpu_vec, 0, node); |