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authorMinghuan Lian <Minghuan.Lian@nxp.com>2016-03-23 19:08:20 +0800
committerMarc Zyngier <marc.zyngier@arm.com>2016-05-04 09:58:04 +0100
commitb8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 (patch)
tree9072b01dd90206a5908274e8d91337c1ca41badf /drivers/irqchip/Kconfig
parent5e79cb29ddbd1d354398308309337ba013245469 (diff)
downloadlinux-b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43.tar.bz2
irqchip: Add Layerscape SCFG MSI controller support
Some kind of Freescale Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/Kconfig')
-rw-r--r--drivers/irqchip/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6c17de7997b9..81f88ada3a61 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -246,5 +246,10 @@ config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
+config LS_SCFG_MSI
+ def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
+ depends on PCI && PCI_MSI
+ select PCI_MSI_IRQ_DOMAIN
+
config PARTITION_PERCPU
bool