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authorDavid Woodhouse <David.Woodhouse@intel.com>2015-10-12 14:17:37 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2015-10-15 12:05:39 +0100
commitb16d0cb9e2fc5c311948c660dd6f4b59a9ccd333 (patch)
tree1f63f7efe5e6607d30372c90aac2275ae8689f9a /drivers/iommu/Kconfig
parent8a94ade4ce6df22006b96c5c9a8d6d12fce67585 (diff)
downloadlinux-b16d0cb9e2fc5c311948c660dd6f4b59a9ccd333.tar.bz2
iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS
The behaviour if you enable PASID support after ATS is undefined. So we have to enable it first, even if we don't know whether we'll need it. This is safe enough; unless we set up a context that permits it, the device can't actually *do* anything with it. Also shift the feature detction to dmar_insert_one_dev_info() as it only needs to happen once. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/iommu/Kconfig')
-rw-r--r--drivers/iommu/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index e3b2c2e62e32..8d23f5ed8ae2 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -138,6 +138,7 @@ config INTEL_IOMMU
config INTEL_IOMMU_SVM
bool "Support for Shared Virtual Memory with Intel IOMMU"
depends on INTEL_IOMMU && X86
+ select PCI_PASID
help
Shared Virtual Memory (SVM) provides a facility for devices
to access DMA resources through process address space by