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authorMichal Simek <michal.simek@xilinx.com>2017-08-31 14:55:45 -0700
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2017-08-31 15:01:30 -0700
commitda1a42cd457fb06c2fd141c670b2ca3397234322 (patch)
tree8ebe86d9f2c6551f69cf6299435f9c3ceaca9352 /drivers/input/serio
parent117b2dc58c07924da7f545f93a1f5862f46e14f7 (diff)
downloadlinux-da1a42cd457fb06c2fd141c670b2ca3397234322.tar.bz2
Input: xilinx_ps2 - fix multiline comment style
Fix multiline comments style not to be reported by checkpatch. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Diffstat (limited to 'drivers/input/serio')
-rw-r--r--drivers/input/serio/xilinx_ps2.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/input/serio/xilinx_ps2.c b/drivers/input/serio/xilinx_ps2.c
index 14c40892ed82..07de1b49293c 100644
--- a/drivers/input/serio/xilinx_ps2.c
+++ b/drivers/input/serio/xilinx_ps2.c
@@ -45,8 +45,10 @@
#define XPS2_STATUS_RX_FULL 0x00000001 /* Receive Full */
#define XPS2_STATUS_TX_FULL 0x00000002 /* Transmit Full */
-/* Bit definitions for ISR/IER registers. Both the registers have the same bit
- * definitions and are only defined once. */
+/*
+ * Bit definitions for ISR/IER registers. Both the registers have the same bit
+ * definitions and are only defined once.
+ */
#define XPS2_IPIXR_WDT_TOUT 0x00000001 /* Watchdog Timeout Interrupt */
#define XPS2_IPIXR_TX_NOACK 0x00000002 /* Transmit No ACK Interrupt */
#define XPS2_IPIXR_TX_ACK 0x00000004 /* Transmit ACK (Data) Interrupt */
@@ -292,8 +294,10 @@ static int xps2_of_probe(struct platform_device *ofdev)
/* Disable all the interrupts, just in case */
out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, 0);
- /* Reset the PS2 device and abort any current transaction, to make sure
- * we have the PS2 in a good state */
+ /*
+ * Reset the PS2 device and abort any current transaction,
+ * to make sure we have the PS2 in a good state.
+ */
out_be32(drvdata->base_address + XPS2_SRST_OFFSET, XPS2_SRST_RESET);
dev_info(dev, "Xilinx PS2 at 0x%08llX mapped to 0x%p, irq=%d\n",