diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-28 12:27:35 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-28 12:27:35 -0700 |
commit | 02e2af20f4f9f2aa0c84e9a30a35c02f0fbb7daa (patch) | |
tree | d126449a7d2ea2270627183f7cebd726fbe56a9d /drivers/iio/frequency | |
parent | ff61bc81b3feebcef4d0431a92e2e40e8d4fe8b3 (diff) | |
parent | 37fd83916da2e4cae03d350015c82a67b1b334c4 (diff) | |
download | linux-02e2af20f4f9f2aa0c84e9a30a35c02f0fbb7daa.tar.bz2 |
Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc and other driver updates from Greg KH:
"Here is the big set of char/misc and other small driver subsystem
updates for 5.18-rc1.
Included in here are merges from driver subsystems which contain:
- iio driver updates and new drivers
- fsi driver updates
- fpga driver updates
- habanalabs driver updates and support for new hardware
- soundwire driver updates and new drivers
- phy driver updates and new drivers
- coresight driver updates
- icc driver updates
Individual changes include:
- mei driver updates
- interconnect driver updates
- new PECI driver subsystem added
- vmci driver updates
- lots of tiny misc/char driver updates
All of these have been in linux-next for a while with no reported
problems"
* tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits)
firmware: google: Properly state IOMEM dependency
kgdbts: fix return value of __setup handler
firmware: sysfb: fix platform-device leak in error path
firmware: stratix10-svc: add missing callback parameter on RSU
arm64: dts: qcom: add non-secure domain property to fastrpc nodes
misc: fastrpc: Add dma handle implementation
misc: fastrpc: Add fdlist implementation
misc: fastrpc: Add helper function to get list and page
misc: fastrpc: Add support to secure memory map
dt-bindings: misc: add fastrpc domain vmid property
misc: fastrpc: check before loading process to the DSP
misc: fastrpc: add secure domain support
dt-bindings: misc: add property to support non-secure DSP
misc: fastrpc: Add support to get DSP capabilities
misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP
misc: fastrpc: separate fastrpc device from channel context
dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells
dt-bindings: nvmem: make "reg" property optional
nvmem: brcm_nvram: parse NVRAM content into NVMEM cells
nvmem: dt-bindings: Fix the error of dt-bindings check
...
Diffstat (limited to 'drivers/iio/frequency')
-rw-r--r-- | drivers/iio/frequency/Kconfig | 20 | ||||
-rw-r--r-- | drivers/iio/frequency/Makefile | 2 | ||||
-rw-r--r-- | drivers/iio/frequency/ad9523.c | 2 | ||||
-rw-r--r-- | drivers/iio/frequency/adf4350.c | 103 | ||||
-rw-r--r-- | drivers/iio/frequency/admv1013.c | 2 | ||||
-rw-r--r-- | drivers/iio/frequency/admv1014.c | 823 | ||||
-rw-r--r-- | drivers/iio/frequency/admv4420.c | 398 |
7 files changed, 1287 insertions, 63 deletions
diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index b44036f843af..f3702f36436c 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -60,6 +60,26 @@ config ADMV1013 To compile this driver as a module, choose M here: the module will be called admv1013. +config ADMV1014 + tristate "Analog Devices ADMV1014 Microwave Downconverter" + depends on SPI && COMMON_CLK && 64BIT + help + Say yes here to build support for Analog Devices ADMV1014 + 24 GHz to 44 GHz, Wideband, Microwave Downconverter. + + To compile this driver as a module, choose M here: the + module will be called admv1014. + +config ADMV4420 + tristate "Analog Devices ADMV4420 K Band Downconverter" + depends on SPI + help + Say yes here to build support for Analog Devices K Band + Downconverter with integrated Fractional-N PLL and VCO. + + To compile this driver as a module, choose M here: the + module will be called admv4420. + config ADRF6780 tristate "Analog Devices ADRF6780 Microwave Upconverter" depends on SPI diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index ae6899856c99..48add732f1d3 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -8,4 +8,6 @@ obj-$(CONFIG_AD9523) += ad9523.o obj-$(CONFIG_ADF4350) += adf4350.o obj-$(CONFIG_ADF4371) += adf4371.o obj-$(CONFIG_ADMV1013) += admv1013.o +obj-$(CONFIG_ADMV1014) += admv1014.o +obj-$(CONFIG_ADMV4420) += admv4420.o obj-$(CONFIG_ADRF6780) += adrf6780.o diff --git a/drivers/iio/frequency/ad9523.c b/drivers/iio/frequency/ad9523.c index bdb0bc3b12dd..a0f92c336fc4 100644 --- a/drivers/iio/frequency/ad9523.c +++ b/drivers/iio/frequency/ad9523.c @@ -551,7 +551,7 @@ static ssize_t ad9523_show(struct device *dev, mutex_lock(&st->lock); ret = ad9523_read(indio_dev, AD9523_READBACK_0); if (ret >= 0) { - ret = sprintf(buf, "%d\n", !!(ret & (1 << + ret = sysfs_emit(buf, "%d\n", !!(ret & (1 << (u32)this_attr->address))); } mutex_unlock(&st->lock); diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c index f3521330f6fb..be1218d86291 100644 --- a/drivers/iio/frequency/adf4350.c +++ b/drivers/iio/frequency/adf4350.c @@ -7,17 +7,18 @@ #include <linux/device.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/property.h> #include <linux/slab.h> #include <linux/sysfs.h> #include <linux/spi/spi.h> #include <linux/regulator/consumer.h> #include <linux/err.h> -#include <linux/module.h> #include <linux/gcd.h> #include <linux/gpio/consumer.h> #include <asm/div64.h> #include <linux/clk.h> -#include <linux/of.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> @@ -381,10 +382,8 @@ static const struct iio_info adf4350_info = { .debugfs_reg_access = &adf4350_reg_access, }; -#ifdef CONFIG_OF static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) { - struct device_node *np = dev->of_node; struct adf4350_platform_data *pdata; unsigned int tmp; @@ -392,101 +391,83 @@ static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) if (!pdata) return NULL; - snprintf(&pdata->name[0], SPI_NAME_SIZE - 1, "%pOFn", np); + snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev)); tmp = 10000; - of_property_read_u32(np, "adi,channel-spacing", &tmp); + device_property_read_u32(dev, "adi,channel-spacing", &tmp); pdata->channel_spacing = tmp; tmp = 0; - of_property_read_u32(np, "adi,power-up-frequency", &tmp); + device_property_read_u32(dev, "adi,power-up-frequency", &tmp); pdata->power_up_frequency = tmp; tmp = 0; - of_property_read_u32(np, "adi,reference-div-factor", &tmp); + device_property_read_u32(dev, "adi,reference-div-factor", &tmp); pdata->ref_div_factor = tmp; - pdata->ref_doubler_en = of_property_read_bool(np, - "adi,reference-doubler-enable"); - pdata->ref_div2_en = of_property_read_bool(np, - "adi,reference-div2-enable"); + pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable"); + pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable"); /* r2_user_settings */ - pdata->r2_user_settings = of_property_read_bool(np, - "adi,phase-detector-polarity-positive-enable") ? - ADF4350_REG2_PD_POLARITY_POS : 0; - pdata->r2_user_settings |= of_property_read_bool(np, - "adi,lock-detect-precision-6ns-enable") ? - ADF4350_REG2_LDP_6ns : 0; - pdata->r2_user_settings |= of_property_read_bool(np, - "adi,lock-detect-function-integer-n-enable") ? - ADF4350_REG2_LDF_INT_N : 0; + pdata->r2_user_settings = 0; + if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable")) + pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS; + if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable")) + pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns; + if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable")) + pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N; tmp = 2500; - of_property_read_u32(np, "adi,charge-pump-current", &tmp); + device_property_read_u32(dev, "adi,charge-pump-current", &tmp); pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); tmp = 0; - of_property_read_u32(np, "adi,muxout-select", &tmp); + device_property_read_u32(dev, "adi,muxout-select", &tmp); pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); - pdata->r2_user_settings |= of_property_read_bool(np, - "adi,low-spur-mode-enable") ? - ADF4350_REG2_NOISE_MODE(0x3) : 0; + if (device_property_read_bool(dev, "adi,low-spur-mode-enable")) + pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3); /* r3_user_settings */ - pdata->r3_user_settings = of_property_read_bool(np, - "adi,cycle-slip-reduction-enable") ? - ADF4350_REG3_12BIT_CSR_EN : 0; - pdata->r3_user_settings |= of_property_read_bool(np, - "adi,charge-cancellation-enable") ? - ADF4351_REG3_CHARGE_CANCELLATION_EN : 0; - - pdata->r3_user_settings |= of_property_read_bool(np, - "adi,anti-backlash-3ns-enable") ? - ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0; - pdata->r3_user_settings |= of_property_read_bool(np, - "adi,band-select-clock-mode-high-enable") ? - ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0; + pdata->r3_user_settings = 0; + if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable")) + pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN; + if (device_property_read_bool(dev, "adi,charge-cancellation-enable")) + pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN; + if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable")) + pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN; + if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable")) + pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH; tmp = 0; - of_property_read_u32(np, "adi,12bit-clk-divider", &tmp); + device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp); pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); tmp = 0; - of_property_read_u32(np, "adi,clk-divider-mode", &tmp); + device_property_read_u32(dev, "adi,clk-divider-mode", &tmp); pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); /* r4_user_settings */ - pdata->r4_user_settings = of_property_read_bool(np, - "adi,aux-output-enable") ? - ADF4350_REG4_AUX_OUTPUT_EN : 0; - pdata->r4_user_settings |= of_property_read_bool(np, - "adi,aux-output-fundamental-enable") ? - ADF4350_REG4_AUX_OUTPUT_FUND : 0; - pdata->r4_user_settings |= of_property_read_bool(np, - "adi,mute-till-lock-enable") ? - ADF4350_REG4_MUTE_TILL_LOCK_EN : 0; + pdata->r4_user_settings = 0; + if (device_property_read_bool(dev, "adi,aux-output-enable")) + pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN; + if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable")) + pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND; + if (device_property_read_bool(dev, "adi,mute-till-lock-enable")) + pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN; tmp = 0; - of_property_read_u32(np, "adi,output-power", &tmp); + device_property_read_u32(dev, "adi,output-power", &tmp); pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); tmp = 0; - of_property_read_u32(np, "adi,aux-output-power", &tmp); + device_property_read_u32(dev, "adi,aux-output-power", &tmp); pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); return pdata; } -#else -static -struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) -{ - return NULL; -} -#endif static int adf4350_probe(struct spi_device *spi) { @@ -496,7 +477,7 @@ static int adf4350_probe(struct spi_device *spi) struct clk *clk = NULL; int ret; - if (spi->dev.of_node) { + if (dev_fwnode(&spi->dev)) { pdata = adf4350_parse_dt(&spi->dev); if (pdata == NULL) return -EINVAL; @@ -623,7 +604,7 @@ MODULE_DEVICE_TABLE(spi, adf4350_id); static struct spi_driver adf4350_driver = { .driver = { .name = "adf4350", - .of_match_table = of_match_ptr(adf4350_of_match), + .of_match_table = adf4350_of_match, }, .probe = adf4350_probe, .remove = adf4350_remove, diff --git a/drivers/iio/frequency/admv1013.c b/drivers/iio/frequency/admv1013.c index 3f3c478e9baa..b0e1f6571afb 100644 --- a/drivers/iio/frequency/admv1013.c +++ b/drivers/iio/frequency/admv1013.c @@ -630,7 +630,7 @@ static int admv1013_probe(struct spi_device *spi) } static const struct spi_device_id admv1013_id[] = { - { "admv1013", 0}, + { "admv1013", 0 }, {} }; MODULE_DEVICE_TABLE(spi, admv1013_id); diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c new file mode 100644 index 000000000000..a7994f8e6b9b --- /dev/null +++ b/drivers/iio/frequency/admv1014.c @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ADMV1014 driver + * + * Copyright 2022 Analog Devices Inc. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/device.h> +#include <linux/iio/iio.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/notifier.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> +#include <linux/units.h> + +#include <asm/unaligned.h> + +/* ADMV1014 Register Map */ +#define ADMV1014_REG_SPI_CONTROL 0x00 +#define ADMV1014_REG_ALARM 0x01 +#define ADMV1014_REG_ALARM_MASKS 0x02 +#define ADMV1014_REG_ENABLE 0x03 +#define ADMV1014_REG_QUAD 0x04 +#define ADMV1014_REG_LO_AMP_PHASE_ADJUST1 0x05 +#define ADMV1014_REG_MIXER 0x07 +#define ADMV1014_REG_IF_AMP 0x08 +#define ADMV1014_REG_IF_AMP_BB_AMP 0x09 +#define ADMV1014_REG_BB_AMP_AGC 0x0A +#define ADMV1014_REG_VVA_TEMP_COMP 0x0B + +/* ADMV1014_REG_SPI_CONTROL Map */ +#define ADMV1014_PARITY_EN_MSK BIT(15) +#define ADMV1014_SPI_SOFT_RESET_MSK BIT(14) +#define ADMV1014_CHIP_ID_MSK GENMASK(11, 4) +#define ADMV1014_CHIP_ID 0x9 +#define ADMV1014_REVISION_ID_MSK GENMASK(3, 0) + +/* ADMV1014_REG_ALARM Map */ +#define ADMV1014_PARITY_ERROR_MSK BIT(15) +#define ADMV1014_TOO_FEW_ERRORS_MSK BIT(14) +#define ADMV1014_TOO_MANY_ERRORS_MSK BIT(13) +#define ADMV1014_ADDRESS_RANGE_ERROR_MSK BIT(12) + +/* ADMV1014_REG_ENABLE Map */ +#define ADMV1014_IBIAS_PD_MSK BIT(14) +#define ADMV1014_P1DB_COMPENSATION_MSK GENMASK(13, 12) +#define ADMV1014_IF_AMP_PD_MSK BIT(11) +#define ADMV1014_QUAD_BG_PD_MSK BIT(9) +#define ADMV1014_BB_AMP_PD_MSK BIT(8) +#define ADMV1014_QUAD_IBIAS_PD_MSK BIT(7) +#define ADMV1014_DET_EN_MSK BIT(6) +#define ADMV1014_BG_PD_MSK BIT(5) + +/* ADMV1014_REG_QUAD Map */ +#define ADMV1014_QUAD_SE_MODE_MSK GENMASK(9, 6) +#define ADMV1014_QUAD_FILTERS_MSK GENMASK(3, 0) + +/* ADMV1014_REG_LO_AMP_PHASE_ADJUST1 Map */ +#define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK GENMASK(15, 9) +#define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK GENMASK(8, 2) + +/* ADMV1014_REG_MIXER Map */ +#define ADMV1014_MIXER_VGATE_MSK GENMASK(15, 9) +#define ADMV1014_DET_PROG_MSK GENMASK(6, 0) + +/* ADMV1014_REG_IF_AMP Map */ +#define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK GENMASK(11, 8) +#define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK GENMASK(7, 4) +#define ADMV1014_IF_AMP_FINE_GAIN_I_MSK GENMASK(3, 0) + +/* ADMV1014_REG_IF_AMP_BB_AMP Map */ +#define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK GENMASK(15, 12) +#define ADMV1014_BB_AMP_OFFSET_Q_MSK GENMASK(9, 5) +#define ADMV1014_BB_AMP_OFFSET_I_MSK GENMASK(4, 0) + +/* ADMV1014_REG_BB_AMP_AGC Map */ +#define ADMV1014_BB_AMP_REF_GEN_MSK GENMASK(6, 3) +#define ADMV1014_BB_AMP_GAIN_CTRL_MSK GENMASK(2, 1) +#define ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK BIT(0) + +/* ADMV1014_REG_VVA_TEMP_COMP Map */ +#define ADMV1014_VVA_TEMP_COMP_MSK GENMASK(15, 0) + +/* ADMV1014 Miscellaneous Defines */ +#define ADMV1014_READ BIT(7) +#define ADMV1014_REG_ADDR_READ_MSK GENMASK(6, 1) +#define ADMV1014_REG_ADDR_WRITE_MSK GENMASK(22, 17) +#define ADMV1014_REG_DATA_MSK GENMASK(16, 1) +#define ADMV1014_NUM_REGULATORS 9 + +enum { + ADMV1014_IQ_MODE, + ADMV1014_IF_MODE, +}; + +enum { + ADMV1014_SE_MODE_POS = 6, + ADMV1014_SE_MODE_NEG = 9, + ADMV1014_SE_MODE_DIFF = 12, +}; + +enum { + ADMV1014_CALIBSCALE_COARSE, + ADMV1014_CALIBSCALE_FINE, +}; + +static const int detector_table[] = {0, 1, 2, 4, 8, 16, 32, 64}; + +static const char * const input_mode_names[] = { "iq", "if" }; + +static const char * const quad_se_mode_names[] = { "se-pos", "se-neg", "diff" }; + +struct admv1014_state { + struct spi_device *spi; + struct clk *clkin; + struct notifier_block nb; + /* Protect against concurrent accesses to the device and to data*/ + struct mutex lock; + struct regulator_bulk_data regulators[ADMV1014_NUM_REGULATORS]; + unsigned int input_mode; + unsigned int quad_se_mode; + unsigned int p1db_comp; + bool det_en; + u8 data[3] ____cacheline_aligned; +}; + +static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114, + 117, 118, 119, 120, 122, 123, 44, 45}; + +static int __admv1014_spi_read(struct admv1014_state *st, unsigned int reg, + unsigned int *val) +{ + struct spi_transfer t = {}; + int ret; + + st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg); + st->data[1] = 0; + st->data[2] = 0; + + t.rx_buf = &st->data[0]; + t.tx_buf = &st->data[0]; + t.len = sizeof(st->data); + + ret = spi_sync_transfer(st->spi, &t, 1); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); + + return ret; +} + +static int admv1014_spi_read(struct admv1014_state *st, unsigned int reg, + unsigned int *val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_read(st, reg, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int __admv1014_spi_write(struct admv1014_state *st, + unsigned int reg, + unsigned int val) +{ + put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) | + FIELD_PREP(ADMV1014_REG_ADDR_WRITE_MSK, reg), &st->data[0]); + + return spi_write(st->spi, &st->data[0], 3); +} + +static int admv1014_spi_write(struct admv1014_state *st, unsigned int reg, + unsigned int val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_write(st, reg, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int __admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, + unsigned int mask, unsigned int val) +{ + unsigned int data, temp; + int ret; + + ret = __admv1014_spi_read(st, reg, &data); + if (ret) + return ret; + + temp = (data & ~mask) | (val & mask); + + return __admv1014_spi_write(st, reg, temp); +} + +static int admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, + unsigned int mask, unsigned int val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_update_bits(st, reg, mask, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int admv1014_update_quad_filters(struct admv1014_state *st) +{ + unsigned int filt_raw; + u64 rate = clk_get_rate(st->clkin); + + if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ)) + filt_raw = 15; + else if (rate > (7000 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ)) + filt_raw = 10; + else if (rate > (8000 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ)) + filt_raw = 5; + else + filt_raw = 0; + + return __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, + ADMV1014_QUAD_FILTERS_MSK, + FIELD_PREP(ADMV1014_QUAD_FILTERS_MSK, filt_raw)); +} + +static int admv1014_update_vcm_settings(struct admv1014_state *st) +{ + unsigned int i, vcm_mv, vcm_comp, bb_sw_hl_cm; + int ret; + + vcm_mv = regulator_get_voltage(st->regulators[0].consumer) / 1000; + for (i = 0; i < ARRAY_SIZE(mixer_vgate_table); i++) { + vcm_comp = 1050 + mult_frac(i, 450, 8); + if (vcm_mv != vcm_comp) + continue; + + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, + ADMV1014_MIXER_VGATE_MSK, + FIELD_PREP(ADMV1014_MIXER_VGATE_MSK, + mixer_vgate_table[i])); + if (ret) + return ret; + + bb_sw_hl_cm = ~(i / 8); + bb_sw_hl_cm = FIELD_PREP(ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, bb_sw_hl_cm); + + return __admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, + ADMV1014_BB_AMP_REF_GEN_MSK | + ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, + FIELD_PREP(ADMV1014_BB_AMP_REF_GEN_MSK, i) | + bb_sw_hl_cm); + } + + return -EINVAL; +} + +static int admv1014_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data; + int ret; + + switch (info) { + case IIO_CHAN_INFO_OFFSET: + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_I_MSK, data); + else + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_Q_MSK, data); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_PHASE: + ret = admv1014_spi_read(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, data); + else + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, data); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret = admv1014_spi_read(st, ADMV1014_REG_MIXER, &data); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_DET_PROG_MSK, data); + return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBSCALE: + ret = admv1014_spi_read(st, ADMV1014_REG_BB_AMP_AGC, &data); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_BB_AMP_GAIN_CTRL_MSK, data); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int admv1014_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + int data; + unsigned int msk; + struct admv1014_state *st = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_OFFSET: + if (chan->channel2 == IIO_MOD_I) { + msk = ADMV1014_BB_AMP_OFFSET_I_MSK; + data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_I_MSK, val); + } else { + msk = ADMV1014_BB_AMP_OFFSET_Q_MSK; + data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_Q_MSK, val); + } + + return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, msk, data); + case IIO_CHAN_INFO_PHASE: + if (chan->channel2 == IIO_MOD_I) { + msk = ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK; + data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, val); + } else { + msk = ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK; + data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, val); + } + + return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, msk, data); + case IIO_CHAN_INFO_SCALE: + return admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, + ADMV1014_DET_PROG_MSK, + FIELD_PREP(ADMV1014_DET_PROG_MSK, val)); + case IIO_CHAN_INFO_CALIBSCALE: + return admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, + ADMV1014_BB_AMP_GAIN_CTRL_MSK, + FIELD_PREP(ADMV1014_BB_AMP_GAIN_CTRL_MSK, val)); + default: + return -EINVAL; + } +} + +static ssize_t admv1014_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data; + int ret; + + switch (private) { + case ADMV1014_CALIBSCALE_COARSE: + if (chan->channel2 == IIO_MOD_I) { + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); + if (ret) + return ret; + + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); + } else { + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); + if (ret) + return ret; + + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); + } + break; + case ADMV1014_CALIBSCALE_FINE: + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); + else + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); + break; + default: + return -EINVAL; + } + + return sysfs_emit(buf, "%u\n", data); +} + +static ssize_t admv1014_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data, addr, msk; + int ret; + + ret = kstrtouint(buf, 10, &data); + if (ret) + return ret; + + switch (private) { + case ADMV1014_CALIBSCALE_COARSE: + if (chan->channel2 == IIO_MOD_I) { + addr = ADMV1014_REG_IF_AMP; + msk = ADMV1014_IF_AMP_COARSE_GAIN_I_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); + } else { + addr = ADMV1014_REG_IF_AMP_BB_AMP; + msk = ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); + } + break; + case ADMV1014_CALIBSCALE_FINE: + addr = ADMV1014_REG_IF_AMP; + + if (chan->channel2 == IIO_MOD_I) { + msk = ADMV1014_IF_AMP_FINE_GAIN_I_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); + } else { + msk = ADMV1014_IF_AMP_FINE_GAIN_Q_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); + } + break; + default: + return -EINVAL; + } + + ret = admv1014_spi_update_bits(st, addr, msk, data); + + return ret ? ret : len; +} + +static int admv1014_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + *vals = detector_table; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(detector_table); + + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int admv1014_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int write_val, + unsigned int *read_val) +{ + struct admv1014_state *st = iio_priv(indio_dev); + + if (read_val) + return admv1014_spi_read(st, reg, read_val); + else + return admv1014_spi_write(st, reg, write_val); +} + +static const struct iio_info admv1014_info = { + .read_raw = admv1014_read_raw, + .write_raw = admv1014_write_raw, + .read_avail = &admv1014_read_avail, + .debugfs_reg_access = &admv1014_reg_access, +}; + +static const char * const admv1014_reg_name[] = { + "vcm", "vcc-if-bb", "vcc-vga", "vcc-vva", "vcc-lna-3p3", + "vcc-lna-1p5", "vcc-bg", "vcc-quad", "vcc-mixer" +}; + +static int admv1014_freq_change(struct notifier_block *nb, unsigned long action, void *data) +{ + struct admv1014_state *st = container_of(nb, struct admv1014_state, nb); + int ret; + + if (action == POST_RATE_CHANGE) { + mutex_lock(&st->lock); + ret = notifier_from_errno(admv1014_update_quad_filters(st)); + mutex_unlock(&st->lock); + return ret; + } + + return NOTIFY_OK; +} + +#define _ADMV1014_EXT_INFO(_name, _shared, _ident) { \ + .name = _name, \ + .read = admv1014_read, \ + .write = admv1014_write, \ + .private = _ident, \ + .shared = _shared, \ +} + +static const struct iio_chan_spec_ext_info admv1014_ext_info[] = { + _ADMV1014_EXT_INFO("calibscale_coarse", IIO_SEPARATE, ADMV1014_CALIBSCALE_COARSE), + _ADMV1014_EXT_INFO("calibscale_fine", IIO_SEPARATE, ADMV1014_CALIBSCALE_FINE), + { } +}; + +#define ADMV1014_CHAN_IQ(_channel, rf_comp) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE), \ + } + +#define ADMV1014_CHAN_IF(_channel, rf_comp) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + } + +#define ADMV1014_CHAN_POWER(_channel) { \ + .type = IIO_POWER, \ + .output = 0, \ + .indexed = 1, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ + } + +#define ADMV1014_CHAN_CALIBSCALE(_channel, rf_comp, _admv1014_ext_info) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .ext_info = _admv1014_ext_info, \ + } + +static const struct iio_chan_spec admv1014_channels_iq[] = { + ADMV1014_CHAN_IQ(0, I), + ADMV1014_CHAN_IQ(0, Q), + ADMV1014_CHAN_POWER(0), +}; + +static const struct iio_chan_spec admv1014_channels_if[] = { + ADMV1014_CHAN_IF(0, I), + ADMV1014_CHAN_IF(0, Q), + ADMV1014_CHAN_CALIBSCALE(0, I, admv1014_ext_info), + ADMV1014_CHAN_CALIBSCALE(0, Q, admv1014_ext_info), + ADMV1014_CHAN_POWER(0), +}; + +static void admv1014_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static void admv1014_reg_disable(void *data) +{ + regulator_bulk_disable(ADMV1014_NUM_REGULATORS, data); +} + +static void admv1014_powerdown(void *data) +{ + unsigned int enable_reg, enable_reg_msk; + + /* Disable all components in the Enable Register */ + enable_reg_msk = ADMV1014_IBIAS_PD_MSK | + ADMV1014_IF_AMP_PD_MSK | + ADMV1014_QUAD_BG_PD_MSK | + ADMV1014_BB_AMP_PD_MSK | + ADMV1014_QUAD_IBIAS_PD_MSK | + ADMV1014_BG_PD_MSK; + + enable_reg = FIELD_PREP(ADMV1014_IBIAS_PD_MSK, 1) | + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 1) | + FIELD_PREP(ADMV1014_QUAD_BG_PD_MSK, 1) | + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 1) | + FIELD_PREP(ADMV1014_QUAD_IBIAS_PD_MSK, 1) | + FIELD_PREP(ADMV1014_BG_PD_MSK, 1); + + admv1014_spi_update_bits(data, ADMV1014_REG_ENABLE, + enable_reg_msk, enable_reg); +} + +static int admv1014_init(struct admv1014_state *st) +{ + unsigned int chip_id, enable_reg, enable_reg_msk; + struct spi_device *spi = st->spi; + int ret; + + ret = regulator_bulk_enable(ADMV1014_NUM_REGULATORS, st->regulators); + if (ret) { + dev_err(&spi->dev, "Failed to enable regulators"); + return ret; + } + + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->regulators); + if (ret) + return ret; + + ret = clk_prepare_enable(st->clkin); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin); + if (ret) + return ret; + + st->nb.notifier_call = admv1014_freq_change; + ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st); + if (ret) + return ret; + + /* Perform a software reset */ + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, + ADMV1014_SPI_SOFT_RESET_MSK, + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1)); + if (ret) { + dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n"); + return ret; + } + + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, + ADMV1014_SPI_SOFT_RESET_MSK, + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0)); + if (ret) { + dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n"); + return ret; + } + + ret = __admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C); + if (ret) { + dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n"); + return ret; + } + + ret = __admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id); + if (ret) + return ret; + + chip_id = FIELD_GET(ADMV1014_CHIP_ID_MSK, chip_id); + if (chip_id != ADMV1014_CHIP_ID) { + dev_err(&spi->dev, "Invalid Chip ID.\n"); + ret = -EINVAL; + return ret; + } + + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, + ADMV1014_QUAD_SE_MODE_MSK, + FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK, + st->quad_se_mode)); + if (ret) { + dev_err(&spi->dev, "Writing Quad SE Mode failed.\n"); + return ret; + } + + ret = admv1014_update_quad_filters(st); + if (ret) { + dev_err(&spi->dev, "Update Quad Filters failed.\n"); + return ret; + } + + ret = admv1014_update_vcm_settings(st); + if (ret) { + dev_err(&spi->dev, "Update VCM Settings failed.\n"); + return ret; + } + + enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK | + ADMV1014_IF_AMP_PD_MSK | + ADMV1014_BB_AMP_PD_MSK | + ADMV1014_DET_EN_MSK; + + enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp ? 3 : 0) | + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, !(st->input_mode)) | + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, st->input_mode) | + FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en); + + return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); +} + +static int admv1014_properties_parse(struct admv1014_state *st) +{ + const char *str; + unsigned int i; + struct spi_device *spi = st->spi; + int ret; + + st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); + + st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-compensation-enable"); + + ret = device_property_read_string(&spi->dev, "adi,input-mode", &str); + if (ret) { + st->input_mode = ADMV1014_IQ_MODE; + } else { + ret = match_string(input_mode_names, ARRAY_SIZE(input_mode_names), str); + if (ret < 0) + return ret; + + st->input_mode = ret; + } + + ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str); + if (ret) { + st->quad_se_mode = ADMV1014_SE_MODE_POS; + } else { + ret = match_string(quad_se_mode_names, ARRAY_SIZE(quad_se_mode_names), str); + if (ret < 0) + return ret; + + st->quad_se_mode = ADMV1014_SE_MODE_POS + (ret * 3); + } + + for (i = 0; i < ADMV1014_NUM_REGULATORS; ++i) + st->regulators[i].supply = admv1014_reg_name[i]; + + ret = devm_regulator_bulk_get(&st->spi->dev, ADMV1014_NUM_REGULATORS, + st->regulators); + if (ret) { + dev_err(&spi->dev, "Failed to request regulators"); + return ret; + } + + st->clkin = devm_clk_get(&spi->dev, "lo_in"); + if (IS_ERR(st->clkin)) + return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), + "failed to get the LO input clock\n"); + + return 0; +} + +static int admv1014_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct admv1014_state *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + + ret = admv1014_properties_parse(st); + if (ret) + return ret; + + indio_dev->info = &admv1014_info; + indio_dev->name = "admv1014"; + + if (st->input_mode == ADMV1014_IQ_MODE) { + indio_dev->channels = admv1014_channels_iq; + indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_iq); + } else { + indio_dev->channels = admv1014_channels_if; + indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_if); + } + + st->spi = spi; + + mutex_init(&st->lock); + + ret = admv1014_init(st); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id admv1014_id[] = { + { "admv1014", 0 }, + {} +}; +MODULE_DEVICE_TABLE(spi, admv1014_id); + +static const struct of_device_id admv1014_of_match[] = { + { .compatible = "adi,admv1014" }, + {} +}; +MODULE_DEVICE_TABLE(of, admv1014_of_match); + +static struct spi_driver admv1014_driver = { + .driver = { + .name = "admv1014", + .of_match_table = admv1014_of_match, + }, + .probe = admv1014_probe, + .id_table = admv1014_id, +}; +module_spi_driver(admv1014_driver); + +MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); +MODULE_DESCRIPTION("Analog Devices ADMV1014"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/frequency/admv4420.c b/drivers/iio/frequency/admv4420.c new file mode 100644 index 000000000000..51134aee8510 --- /dev/null +++ b/drivers/iio/frequency/admv4420.c @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* + * ADMV4420 + * + * Copyright 2021 Analog Devices Inc. + */ + +#include <linux/bitfield.h> +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/spi/spi.h> +#include <linux/units.h> + +#include <asm/unaligned.h> + +/* ADMV4420 Register Map */ +#define ADMV4420_SPI_CONFIG_1 0x00 +#define ADMV4420_SPI_CONFIG_2 0x01 +#define ADMV4420_CHIPTYPE 0x03 +#define ADMV4420_PRODUCT_ID_L 0x04 +#define ADMV4420_PRODUCT_ID_H 0x05 +#define ADMV4420_SCRATCHPAD 0x0A +#define ADMV4420_SPI_REV 0x0B +#define ADMV4420_ENABLES 0x103 +#define ADMV4420_SDO_LEVEL 0x108 +#define ADMV4420_INT_L 0x200 +#define ADMV4420_INT_H 0x201 +#define ADMV4420_FRAC_L 0x202 +#define ADMV4420_FRAC_M 0x203 +#define ADMV4420_FRAC_H 0x204 +#define ADMV4420_MOD_L 0x208 +#define ADMV4420_MOD_M 0x209 +#define ADMV4420_MOD_H 0x20A +#define ADMV4420_R_DIV_L 0x20C +#define ADMV4420_R_DIV_H 0x20D +#define ADMV4420_REFERENCE 0x20E +#define ADMV4420_VCO_DATA_READBACK1 0x211 +#define ADMV4420_VCO_DATA_READBACK2 0x212 +#define ADMV4420_PLL_MUX_SEL 0x213 +#define ADMV4420_LOCK_DETECT 0x214 +#define ADMV4420_BAND_SELECT 0x215 +#define ADMV4420_VCO_ALC_TIMEOUT 0x216 +#define ADMV4420_VCO_MANUAL 0x217 +#define ADMV4420_ALC 0x219 +#define ADMV4420_VCO_TIMEOUT1 0x21C +#define ADMV4420_VCO_TIMEOUT2 0x21D +#define ADMV4420_VCO_BAND_DIV 0x21E +#define ADMV4420_VCO_READBACK_SEL 0x21F +#define ADMV4420_AUTOCAL 0x226 +#define ADMV4420_CP_STATE 0x22C +#define ADMV4420_CP_BLEED_EN 0x22D +#define ADMV4420_CP_CURRENT 0x22E +#define ADMV4420_CP_BLEED 0x22F + +#define ADMV4420_SPI_CONFIG_1_SDOACTIVE (BIT(4) | BIT(3)) +#define ADMV4420_SPI_CONFIG_1_ENDIAN (BIT(5) | BIT(2)) +#define ADMV4420_SPI_CONFIG_1_SOFTRESET (BIT(7) | BIT(1)) + +#define ADMV4420_REFERENCE_DIVIDE_BY_2_MASK BIT(0) +#define ADMV4420_REFERENCE_MODE_MASK BIT(1) +#define ADMV4420_REFERENCE_DOUBLER_MASK BIT(2) + +#define ADMV4420_REF_DIVIDER_MAX_VAL GENMASK(9, 0) +#define ADMV4420_N_COUNTER_INT_MAX GENMASK(15, 0) +#define ADMV4420_N_COUNTER_FRAC_MAX GENMASK(23, 0) +#define ADMV4420_N_COUNTER_MOD_MAX GENMASK(23, 0) + +#define ENABLE_PLL BIT(6) +#define ENABLE_LO BIT(5) +#define ENABLE_VCO BIT(3) +#define ENABLE_IFAMP BIT(2) +#define ENABLE_MIXER BIT(1) +#define ENABLE_LNA BIT(0) + +#define ADMV4420_SCRATCH_PAD_VAL_1 0xAD +#define ADMV4420_SCRATCH_PAD_VAL_2 0xEA + +#define ADMV4420_REF_FREQ_HZ 50000000 +#define MAX_N_COUNTER 655360UL +#define MAX_R_DIVIDER 1024 +#define ADMV4420_DEFAULT_LO_FREQ_HZ 16750000000ULL + +enum admv4420_mux_sel { + ADMV4420_LOW = 0, + ADMV4420_LOCK_DTCT = 1, + ADMV4420_R_COUNTER_PER_2 = 4, + ADMV4420_N_CONUTER_PER_2 = 5, + ADMV4420_HIGH = 8, +}; + +struct admv4420_reference_block { + bool doubler_en; + bool divide_by_2_en; + bool ref_single_ended; + u32 divider; +}; + +struct admv4420_n_counter { + u32 int_val; + u32 frac_val; + u32 mod_val; + u32 n_counter; +}; + +struct admv4420_state { + struct spi_device *spi; + struct regmap *regmap; + u64 vco_freq_hz; + u64 lo_freq_hz; + struct admv4420_reference_block ref_block; + struct admv4420_n_counter n_counter; + enum admv4420_mux_sel mux_sel; + struct mutex lock; + u8 transf_buf[4] ____cacheline_aligned; +}; + +static const struct regmap_config admv4420_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .read_flag_mask = BIT(7), +}; + +static int admv4420_reg_access(struct iio_dev *indio_dev, + u32 reg, u32 writeval, + u32 *readval) +{ + struct admv4420_state *st = iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + else + return regmap_write(st->regmap, reg, writeval); +} + +static int admv4420_set_n_counter(struct admv4420_state *st, u32 int_val, + u32 frac_val, u32 mod_val) +{ + int ret; + + put_unaligned_le32(frac_val, st->transf_buf); + ret = regmap_bulk_write(st->regmap, ADMV4420_FRAC_L, st->transf_buf, 3); + if (ret) + return ret; + + put_unaligned_le32(mod_val, st->transf_buf); + ret = regmap_bulk_write(st->regmap, ADMV4420_MOD_L, st->transf_buf, 3); + if (ret) + return ret; + + put_unaligned_le32(int_val, st->transf_buf); + return regmap_bulk_write(st->regmap, ADMV4420_INT_L, st->transf_buf, 2); +} + +static int admv4420_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct admv4420_state *st = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_FREQUENCY: + + *val = div_u64_rem(st->lo_freq_hz, MICRO, val2); + + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static const struct iio_info admv4420_info = { + .read_raw = admv4420_read_raw, + .debugfs_reg_access = &admv4420_reg_access, +}; + +static const struct iio_chan_spec admv4420_channels[] = { + { + .type = IIO_ALTVOLTAGE, + .output = 0, + .indexed = 1, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_FREQUENCY), + }, +}; + +static void admv4420_fw_parse(struct admv4420_state *st) +{ + struct device *dev = &st->spi->dev; + u32 tmp; + int ret; + + ret = device_property_read_u32(dev, "adi,lo-freq-khz", &tmp); + if (!ret) + st->lo_freq_hz = (u64)tmp * KILO; + + st->ref_block.ref_single_ended = device_property_read_bool(dev, + "adi,ref-ext-single-ended-en"); +} + +static inline uint64_t admv4420_calc_pfd_vco(struct admv4420_state *st) +{ + return div_u64(st->vco_freq_hz * 10, st->n_counter.n_counter); +} + +static inline uint32_t admv4420_calc_pfd_ref(struct admv4420_state *st) +{ + uint32_t tmp; + u8 doubler, divide_by_2; + + doubler = st->ref_block.doubler_en ? 2 : 1; + divide_by_2 = st->ref_block.divide_by_2_en ? 2 : 1; + tmp = ADMV4420_REF_FREQ_HZ * doubler; + + return (tmp / (st->ref_block.divider * divide_by_2)); +} + +static int admv4420_calc_parameters(struct admv4420_state *st) +{ + u64 pfd_ref, pfd_vco; + bool sol_found = false; + + st->ref_block.doubler_en = false; + st->ref_block.divide_by_2_en = false; + st->vco_freq_hz = div_u64(st->lo_freq_hz, 2); + + for (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER; + st->ref_block.divider++) { + pfd_ref = admv4420_calc_pfd_ref(st); + for (st->n_counter.n_counter = 1; st->n_counter.n_counter < MAX_N_COUNTER; + st->n_counter.n_counter++) { + pfd_vco = admv4420_calc_pfd_vco(st); + if (pfd_ref == pfd_vco) { + sol_found = true; + break; + } + } + + if (sol_found) + break; + + st->n_counter.n_counter = 1; + } + if (!sol_found) + return -1; + + st->n_counter.int_val = div_u64_rem(st->n_counter.n_counter, 10, &st->n_counter.frac_val); + st->n_counter.mod_val = 10; + + return 0; +} + +static int admv4420_setup(struct iio_dev *indio_dev) +{ + struct admv4420_state *st = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; + u32 val; + int ret; + + ret = regmap_write(st->regmap, ADMV4420_SPI_CONFIG_1, + ADMV4420_SPI_CONFIG_1_SOFTRESET); + if (ret) + return ret; + + ret = regmap_write(st->regmap, ADMV4420_SPI_CONFIG_1, + ADMV4420_SPI_CONFIG_1_SDOACTIVE | + ADMV4420_SPI_CONFIG_1_ENDIAN); + if (ret) + return ret; + + ret = regmap_write(st->regmap, + ADMV4420_SCRATCHPAD, + ADMV4420_SCRATCH_PAD_VAL_1); + if (ret) + return ret; + + ret = regmap_read(st->regmap, ADMV4420_SCRATCHPAD, &val); + if (ret) + return ret; + + if (val != ADMV4420_SCRATCH_PAD_VAL_1) { + dev_err(dev, "Failed ADMV4420 to read/write scratchpad %x ", val); + return -EIO; + } + + ret = regmap_write(st->regmap, + ADMV4420_SCRATCHPAD, + ADMV4420_SCRATCH_PAD_VAL_2); + if (ret) + return ret; + + ret = regmap_read(st->regmap, ADMV4420_SCRATCHPAD, &val); + if (ret) + return ret; + + if (val != ADMV4420_SCRATCH_PAD_VAL_2) { + dev_err(dev, "Failed to read/write scratchpad %x ", val); + return -EIO; + } + + st->mux_sel = ADMV4420_LOCK_DTCT; + st->lo_freq_hz = ADMV4420_DEFAULT_LO_FREQ_HZ; + + admv4420_fw_parse(st); + + ret = admv4420_calc_parameters(st); + if (ret) { + dev_err(dev, "Failed calc parameters for %lld ", st->vco_freq_hz); + return ret; + } + + ret = regmap_write(st->regmap, ADMV4420_R_DIV_L, + FIELD_GET(0xFF, st->ref_block.divider)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, ADMV4420_R_DIV_H, + FIELD_GET(0xFF00, st->ref_block.divider)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, ADMV4420_REFERENCE, + st->ref_block.divide_by_2_en | + FIELD_PREP(ADMV4420_REFERENCE_MODE_MASK, st->ref_block.ref_single_ended) | + FIELD_PREP(ADMV4420_REFERENCE_DOUBLER_MASK, st->ref_block.doubler_en)); + if (ret) + return ret; + + ret = admv4420_set_n_counter(st, st->n_counter.int_val, + st->n_counter.frac_val, + st->n_counter.mod_val); + if (ret) + return ret; + + ret = regmap_write(st->regmap, ADMV4420_PLL_MUX_SEL, st->mux_sel); + if (ret) + return ret; + + return regmap_write(st->regmap, ADMV4420_ENABLES, + ENABLE_PLL | ENABLE_LO | ENABLE_VCO | + ENABLE_IFAMP | ENABLE_MIXER | ENABLE_LNA); +} + +static int admv4420_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct admv4420_state *st; + struct regmap *regmap; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + regmap = devm_regmap_init_spi(spi, &admv4420_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(regmap), + "Failed to initializing spi regmap\n"); + + st = iio_priv(indio_dev); + st->spi = spi; + st->regmap = regmap; + + indio_dev->name = "admv4420"; + indio_dev->info = &admv4420_info; + indio_dev->channels = admv4420_channels; + indio_dev->num_channels = ARRAY_SIZE(admv4420_channels); + + ret = admv4420_setup(indio_dev); + if (ret) { + dev_err(&spi->dev, "Setup ADMV4420 failed (%d)\n", ret); + return ret; + } + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id admv4420_of_match[] = { + { .compatible = "adi,admv4420" }, + { } +}; + +MODULE_DEVICE_TABLE(of, admv4420_of_match); + +static struct spi_driver admv4420_driver = { + .driver = { + .name = "admv4420", + .of_match_table = admv4420_of_match, + }, + .probe = admv4420_probe, +}; + +module_spi_driver(admv4420_driver); + +MODULE_AUTHOR("Cristian Pop <cristian.pop@analog.com>"); +MODULE_DESCRIPTION("Analog Devices ADMV44200 K Band Downconverter"); +MODULE_LICENSE("Dual BSD/GPL"); |