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authorAlexander Sverdlin <alexander.sverdlin@nokia.com>2015-09-14 11:03:50 +0200
committerWolfram Sang <wsa@the-dreams.de>2015-10-20 17:05:16 +0200
commit35780e860f7d4a5f33f6ceadf09038ee26f1ef43 (patch)
tree341806deefeefb2ceafe960d7ca3880170baf3cf /drivers/i2c/busses
parent064181b00e33c917145194247b4abcfa36ca06d7 (diff)
downloadlinux-35780e860f7d4a5f33f6ceadf09038ee26f1ef43.tar.bz2
i2c: davinci: Optimize clock generation on Keystone SoC
According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed additive part of frequency divisors (referred as "d" in the code and datasheet) always equals to 6, independent of module clock prescaler. module clock frequency master clock frequency = ---------------------- (ICCL + 6) + (ICCH + 6) It was not the case with original Davinci IP. Introduce new compatible property "ti,keystone-i2c", which triggers special handling in the driver. Without this change Keystone-based systems (having 204.8MHz input clock) choose prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz. This gives ~11% transfer rate increase. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com> Tested-by: Lukasz Gemborowski <lukasz.gemborowski@nokia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses')
-rw-r--r--drivers/i2c/busses/i2c-davinci.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 3fbb9a035532..c5628a42170a 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -181,6 +181,7 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
u32 clkh;
u32 clkl;
u32 input_clock = clk_get_rate(dev->clk);
+ struct device_node *of_node = dev->dev->of_node;
/* NOTE: I2C Clock divider programming info
* As per I2C specs the following formulas provide prescaler
@@ -196,6 +197,9 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
* where if PSC == 0, d = 7,
* if PSC == 1, d = 6
* if PSC > 1 , d = 5
+ *
+ * Note:
+ * d is always 6 on Keystone I2C controller
*/
/* get minimum of 7 MHz clock, but max of 12 MHz */
@@ -204,6 +208,9 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
psc++; /* better to run under spec than over */
d = (psc >= 2) ? 5 : 7 - psc;
+ if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
+ d = 6;
+
clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
/* Avoid driving the bus too fast because of rounding errors above */
if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
@@ -726,6 +733,7 @@ static struct i2c_algorithm i2c_davinci_algo = {
static const struct of_device_id davinci_i2c_of_match[] = {
{.compatible = "ti,davinci-i2c", },
+ {.compatible = "ti,keystone-i2c", },
{},
};
MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);