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authorAl Viro <viro@zeniv.linux.org.uk>2016-01-04 10:25:34 -0500
committerAl Viro <viro@zeniv.linux.org.uk>2016-01-04 10:25:34 -0500
commit7e935c7ca1e6c398f11edac5beabfc4348e3b3a4 (patch)
tree86da864ba6341bd86b5f5450c611f918722237b2 /drivers/i2c/busses/i2c-davinci.c
parentc62432b40b5e03c25faf2c8f8547bba4908b8945 (diff)
parente9d408e107db9a554b36c3a79f67b37dd3e16da0 (diff)
downloadlinux-7e935c7ca1e6c398f11edac5beabfc4348e3b3a4.tar.bz2
Merge branch 'memdup_user_nul' into work.misc
Diffstat (limited to 'drivers/i2c/busses/i2c-davinci.c')
-rw-r--r--drivers/i2c/busses/i2c-davinci.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index c5628a42170a..a8bdcb5292f5 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -202,8 +202,15 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
* d is always 6 on Keystone I2C controller
*/
- /* get minimum of 7 MHz clock, but max of 12 MHz */
- psc = (input_clock / 7000000) - 1;
+ /*
+ * Both Davinci and current Keystone User Guides recommend a value
+ * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
+ * always produce enough margin between SDA and SCL transitions.
+ * Measurements show that the higher the module clock is, the
+ * bigger is the margin, providing more reliable communication.
+ * So we better target for 12MHz.
+ */
+ psc = (input_clock / 12000000) - 1;
if ((input_clock / (psc + 1)) > 12000000)
psc++; /* better to run under spec than over */
d = (psc >= 2) ? 5 : 7 - psc;