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author | Stefan Popa <stefan.popa@analog.com> | 2018-05-18 18:23:34 +0300 |
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committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2018-05-20 11:45:45 +0100 |
commit | 1dbae4c6cdeccf87767003a9d3b6d24b40446100 (patch) | |
tree | 986c1cec61bea81eaaa86421d2728d606be05531 /drivers/hid/hid-lgff.c | |
parent | be1b24d2454117113260f2fe59a427d01de4e131 (diff) | |
download | linux-1dbae4c6cdeccf87767003a9d3b6d24b40446100.tar.bz2 |
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/hid/hid-lgff.c')
0 files changed, 0 insertions, 0 deletions