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authorAndrzej Hajda <a.hajda@samsung.com>2015-07-09 10:07:53 +0200
committerInki Dae <inki.dae@samsung.com>2015-08-11 17:21:34 +0900
commit9859e203713a190f79959681836da34606d0d5bd (patch)
treeacbd49604401ccd7661f8f8ee746102d61d3dfaa /drivers/gpu
parente6e771dc05b07be1e2b6ced3fa764b30bdda517d (diff)
downloadlinux-9859e203713a190f79959681836da34606d0d5bd.tar.bz2
drm/exynos/mixer: fix interrupt clearing
The driver used incorrect flags to clear interrupt status. The patch fixes it. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index cae98db33062..25f0aac01a89 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* handling VSYNC */
if (val & MXR_INT_STATUS_VSYNC) {
+ /* vsync interrupt use different bit for read and clear */
+ val |= MXR_INT_CLEAR_VSYNC;
+ val &= ~MXR_INT_STATUS_VSYNC;
+
/* interlace scan need to check shadow register */
if (ctx->interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
out:
/* clear interrupts */
- if (~val & MXR_INT_EN_VSYNC) {
- /* vsync interrupt use different bit for read and clear */
- val &= ~MXR_INT_EN_VSYNC;
- val |= MXR_INT_CLEAR_VSYNC;
- }
mixer_reg_write(res, MXR_INT_STATUS, val);
spin_unlock(&res->reg_slock);