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authorImre Deak <imre.deak@intel.com>2014-04-03 20:02:42 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-04-04 09:30:52 +0200
commit09c87db8b499da5fc5e474a665559a26aecd7c7f (patch)
treeb21311272a80b32147f7802afb3c1bd711b06369 /drivers/gpu
parentf6d519481b662d9fc52836e6e6107520f03e0122 (diff)
downloadlinux-09c87db8b499da5fc5e474a665559a26aecd7c7f.tar.bz2
drm/i915: vlv: fix RPS interrupt mask setting
This typo may lead to missed RPS interrupts and as a result a too low or too high frequency for the current workload. The interrupt mask will be set properly at a subsequent GPU idle event, but can get corrupted again at the next RPS up/down event. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b20a26584e06..f18dec071df7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3159,7 +3159,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
if (val != dev_priv->rps.cur_freq)
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
- I915_WRITE(GEN6_PMINTRMSK, val);
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
dev_priv->rps.cur_freq = val;
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));