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| author | Ben Skeggs <bskeggs@redhat.com> | 2014-06-03 14:48:18 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-06-11 16:11:28 +1000 |
| commit | c33ba689e54d91bac52a6f7a86d06699c9a8e7c3 (patch) | |
| tree | 61afe38f8d4e694b3b2ee9e9ef055ac61ce256dd /drivers/gpu | |
| parent | 3e1eb5cf7c25dee269b9873588a8beecc7a7265a (diff) | |
| download | linux-c33ba689e54d91bac52a6f7a86d06699c9a8e7c3.tar.bz2 | |
drm/nouveau/disp/dp: make use of postcursor when its available
And at the same time, obey the spec better wrt out-of-range requests.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/dport.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c index c2bf611db593..39562d48101d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c @@ -130,18 +130,28 @@ dp_link_train_commit(struct dp_state *dp, bool pc) for (i = 0; i < dp->link_nr; i++) { u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; + u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3; u8 lpre = (lane & 0x0c) >> 2; u8 lvsw = (lane & 0x03) >> 0; + u8 hivs = 3 - lpre; + u8 hipe = 3; + u8 hipc = 3; + + if (lpc2 >= hipc) + lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED; + if (lpre >= hipe) { + lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */ + lvsw = hivs = 3 - (lpre & 3); + } else + if (lvsw >= hivs) { + lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED; + } dp->conf[i] = (lpre << 3) | lvsw; - if (lvsw == 3) - dp->conf[i] |= DPCD_LC03_MAX_SWING_REACHED; - if (lpre == 3) - dp->conf[i] |= DPCD_LC03_MAX_PRE_EMPHASIS_REACHED; - dp->pc2conf[i >> 1] |= 4 << ((i & 1) * 4); - - DBG("config lane %d %02x\n", i, dp->conf[i]); - impl->drv_ctl(outp, i, lvsw, lpre, 0); + dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); + + DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2); + impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3); } ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4); |