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authorJani Nikula <jani.nikula@intel.com>2014-05-14 13:02:19 +0300
committerJani Nikula <jani.nikula@intel.com>2014-05-15 11:04:21 +0300
commitf4cdbc21444a45d207a8dc175f44d2facfbd0845 (patch)
tree6dce3dadce11603c059d17a2dc9ac5360b1dce87 /drivers/gpu
parent05adaf1f101f25f40f12c29403e6488f0e45f6b6 (diff)
downloadlinux-f4cdbc21444a45d207a8dc175f44d2facfbd0845.tar.bz2
drm/i915/dp: force eDP lane count to max available lanes on BDW
There are certain BDW high res eDP machines that regressed due to commit 38aecea0ccbb909d635619cba22f1891e589b434 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Mar 3 11:18:10 2014 +0100 drm/i915: reverse dp link param selection, prefer fast over wide again The commit lead to 2 lanes at 5.4 Gbps being used instead of 4 lanes at 2.7 Gbps on the affected machines. Link training succeeded for both, but the screen remained blank with the former config. Further investigation showed that 4 lanes at 5.4 Gbps worked also. The root cause for the blank screen using 2 lanes remains unknown, but apparently the driver for a certain other operating system by default uses the max available lanes. Follow suit on Broadwell eDP, for at least until we figure out what is going on. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76711 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Tested-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8233f2aea665..2a00cb828d20 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -810,7 +810,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bpp = dev_priv->vbt.edp_bpp;
}
- if (dev_priv->vbt.edp_lanes) {
+ if (IS_BROADWELL(dev)) {
+ /* Yes, it's an ugly hack. */
+ min_lane_count = max_lane_count;
+ DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
+ min_lane_count);
+ } else if (dev_priv->vbt.edp_lanes) {
min_lane_count = min(dev_priv->vbt.edp_lanes,
max_lane_count);
DRM_DEBUG_KMS("using min %u lanes per VBT\n",