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authorAlex Deucher <alexander.deucher@amd.com>2016-02-18 11:10:09 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-22 11:30:35 -0500
commit04ab3b7622a618ea081d17427c15a292710b40cb (patch)
tree3dc33c1f737ad461953bcf16a657780e754a2c02 /drivers/gpu
parente1d09dc0ccc6c91e3916476f636edb76da1f65bb (diff)
downloadlinux-04ab3b7622a618ea081d17427c15a292710b40cb.tar.bz2
drm/amdgpu/gfx8: fix priv reg interrupt enable
Looks like a copy/paste typo. Reviewed-by: Christian König <christian.koenig@amd.com> Noticed-by: David Panariti <David.Panariti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8f8ec37ecd88..1c40bd90afbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4995,7 +4995,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
case AMDGPU_IRQ_STATE_ENABLE:
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
- PRIV_REG_INT_ENABLE, 0);
+ PRIV_REG_INT_ENABLE, 1);
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
break;
default: