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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-23 11:30:55 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-24 17:54:14 +0200
commit0af78a2bb4296839cfe7a855cd128e8687e77bc1 (patch)
tree0f77a0d0a2fc06d6afb10e6bf01ba8690ddfaefe /drivers/gpu
parent9589919fb3d269d4202a112b197468c7db1f97a3 (diff)
downloadlinux-0af78a2bb4296839cfe7a855cd128e8687e77bc1.tar.bz2
drm/i915: reject doubleclocked cea modes on dp
These are ultra-low-res modes used to upscale SDTV content and we don't know how to support these on dp on intel hw: - It's unclear whether we can send avi infoframes over dp ports. - And the pixel repeat setting that work for hdmi/sdvo explicitly don't work for dp. So don't bother and just reject these modes. These modes have been introduced in commit 54ac76f851a1789b047b74a8e14980f2dd1ac749 Author: Christian Schmidt <schmidt@digadd.de> Date: Mon Dec 19 14:53:16 2011 +0000 drm/edid: support CEA video modes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45729 Tested-by: Yuang Guang <guang.a.yang@intel.com> Cc: stable@vger.kernel.org Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3bbd7540bcd8..eb57ec7b36f4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -266,6 +266,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->clock < 10000)
return MODE_CLOCK_LOW;
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_H_ILLEGAL;
+
return MODE_OK;
}
@@ -702,6 +705,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
mode->clock = intel_dp->panel_fixed_mode->clock;
}
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return false;
+
DRM_DEBUG_KMS("DP link computation with max lane count %i "
"max bw %02x pixel clock %iKHz\n",
max_lane_count, bws[max_clock], mode->clock);