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authorChristian König <deathsimple@vodafone.de>2013-04-08 12:41:37 +0200
committerAlex Deucher <alexander.deucher@amd.com>2013-04-09 10:31:39 -0400
commit9a21059dc4c0e80f2eebcb0a9096721ef1dc9c9d (patch)
tree7f116f62ca35fd09d2cf3949dcf27557ff50060b /drivers/gpu/drm/radeon/rv770.c
parentec5891fbe1b078b191b25a13a2cc40b58fb7a693 (diff)
downloadlinux-9a21059dc4c0e80f2eebcb0a9096721ef1dc9c9d.tar.bz2
drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r--drivers/gpu/drm/radeon/rv770.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index c8a5e67d7cda..7bce3b8ba50b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
+ if (rdev->family == CHIP_RV730) {
+ WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
+ WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
+ WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
+ }
WREG32(CGTS_SYS_TCC_DISABLE, 0);
WREG32(CGTS_TCC_DISABLE, 0);