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| author | Dave Airlie <airlied@redhat.com> | 2013-05-21 09:42:55 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2013-05-21 09:42:55 +1000 |
| commit | cc3e06a57d4314ca0582fcf7d6b56dea5ca11f77 (patch) | |
| tree | 9e873aa6e1fdd4dbb72211ba259462c1262352f9 /drivers/gpu/drm/radeon/radeon_bios.c | |
| parent | a3f6902672c9fa3868722ef6ab8a7dd9141def6a (diff) | |
| parent | 2a0f90551a76a626fd6a606877c8635f52f066e6 (diff) | |
| download | linux-cc3e06a57d4314ca0582fcf7d6b56dea5ca11f77.tar.bz2 | |
Merge branch 'drm-fixes-3.10-sun' of git://people.freedesktop.org/~agd5f/linux into drm-next
This is the pull request for AMD Sun/Hainan support. I've
split it out separately from my regular fixes stream. Hainan
is a new SI asic with no UVD or DCE hardware. The patches are
minimally invasive; basically just pci ids and skipping UVD and
DCE init for this family. Most of the changes to si.c are just
the golden register tables for the family.
* 'drm-fixes-3.10-sun' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: add Hainan pci ids
drm/radeon: add golden register settings for Hainan (v2)
drm/radeon: sun/hainan chips do not have UVD (v2)
drm/radeon: track which asics have UVD
drm/radeon: radeon-asic updates for Hainan
drm/radeon: fill in ucode loading support for Hainan
drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
drm/radeon: fill in GPU init for Hainan (v2)
drm/radeon: add chip family for Hainan
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_bios.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_bios.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index b8015913d382..9448cbfd5763 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c @@ -221,24 +221,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev) /* enable the rom */ WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); - /* Disable VGA mode */ - WREG32(AVIVO_D1VGA_CONTROL, - (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - WREG32(AVIVO_D2VGA_CONTROL, - (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - WREG32(AVIVO_VGA_RENDER_CONTROL, - (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + if (!ASIC_IS_NODCE(rdev)) { + /* Disable VGA mode */ + WREG32(AVIVO_D1VGA_CONTROL, + (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + WREG32(AVIVO_D2VGA_CONTROL, + (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + WREG32(AVIVO_VGA_RENDER_CONTROL, + (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + } WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); r = radeon_read_bios(rdev); /* restore regs */ WREG32(R600_BUS_CNTL, bus_cntl); - WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); - WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); - WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + if (!ASIC_IS_NODCE(rdev)) { + WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); + WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); + WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + } WREG32(R600_ROM_CNTL, rom_cntl); return r; } |