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authorAlex Deucher <alexander.deucher@amd.com>2013-08-19 11:06:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:31:00 -0400
commit0b31e02363b0db4e7931561bc6c141436e729d9f (patch)
treeaa4e98b8d2efcedb78561549b4a37e72dd08be65 /drivers/gpu/drm/radeon/evergreend.h
parente5b9e7503eb1f4884efa3b321d3cc47806779202 (diff)
downloadlinux-0b31e02363b0db4e7931561bc6c141436e729d9f.tar.bz2
drm/radeon: update line buffer allocation for dce4.1/5
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce4.1/5 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 430997a70acc..8768fd6a1e27 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1160,6 +1160,10 @@
# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
+#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
+# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
+# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
+
#define IH_RB_CNTL 0x3e00
# define IH_RB_ENABLE (1 << 0)
# define IH_IB_SIZE(x) ((x) << 1) /* log2 */