diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-07-17 14:02:31 -0400 |
|---|---|---|
| committer | Christian König <deathsimple@vodafone.de> | 2012-07-18 13:53:17 +0200 |
| commit | 89d35807fb0fe53b84e88e759cc39107a6195e5f (patch) | |
| tree | afb2e2cb9439239e6f83ad339ad624f42d012adc /drivers/gpu/drm/radeon/evergreen.c | |
| parent | 8b25ed3482885e5f1dc65ace796e90f879d76c52 (diff) | |
| download | linux-89d35807fb0fe53b84e88e759cc39107a6195e5f.tar.bz2 | |
drm/radeon: update rptr saving logic for memory buffers
Add support for using memory buffers rather than
scratch registers. Some rings may not be able to
write to scratch registers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 4b8e5c5fcf84..870009ad5f56 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1364,17 +1364,25 @@ void evergreen_mc_program(struct radeon_device *rdev) void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { struct radeon_ring *ring = &rdev->ring[ib->ring]; + u32 next_rptr; /* set to DX10/11 mode */ radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); radeon_ring_write(ring, 1); if (ring->rptr_save_reg) { - uint32_t next_rptr = ring->wptr + 3 + 4; + next_rptr = ring->wptr + 3 + 4; radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write(ring, ((ring->rptr_save_reg - PACKET3_SET_CONFIG_REG_START) >> 2)); radeon_ring_write(ring, next_rptr); + } else if (rdev->wb.enabled) { + next_rptr = ring->wptr + 5 + 4; + radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); + radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); + radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); + radeon_ring_write(ring, next_rptr); + radeon_ring_write(ring, 0); } radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |