summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/cik.c
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2013-06-03 11:21:58 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 10:49:09 -0400
commit2615b53acec2e0636c9d24a9e82f34904d8e39fd (patch)
tree68c7a7c82a423d50e3cc80171f0f841125cf6958 /drivers/gpu/drm/radeon/cik.c
parent963e81f9e060113d3bec1aa95eac76a7d3810879 (diff)
downloadlinux-2615b53acec2e0636c9d24a9e82f34904d8e39fd.tar.bz2
drm/radeon/cik: switch to type3 nop packet for compute rings (v2)
Type 2 packets are deprecated on CIK MEC and we should use type 3 nop packets. Setting the count field to the max value (0x3fff) indicates that only one dword should be skipped like a type 2 packet. v2: add comment to code Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r--drivers/gpu/drm/radeon/cik.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index c718a9ea5048..19a6b3c31304 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5467,10 +5467,11 @@ static int cik_startup(struct radeon_device *rdev)
return r;
/* set up the compute queues */
+ /* type-2 packets are deprecated on MEC, use type-3 instead */
ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
- 0, 0xfffff, RADEON_CP_PACKET2);
+ 0, 0xfffff, PACKET3(PACKET3_NOP, 0x3FFF));
if (r)
return r;
ring->me = 1; /* first MEC */
@@ -5478,10 +5479,11 @@ static int cik_startup(struct radeon_device *rdev)
ring->queue = 0; /* first queue */
ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
+ /* type-2 packets are deprecated on MEC, use type-3 instead */
ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
- 0, 0xffffffff, RADEON_CP_PACKET2);
+ 0, 0xffffffff, PACKET3(PACKET3_NOP, 0x3FFF));
if (r)
return r;
/* dGPU only have 1 MEC */